ASP-DAC 2000 Advance Technical Program

OPENING SESSION:

Opening Remarks

Kenji Yoshida

General Chair

Awards

Best Papers, University LSI Design Contest

Keynote Address I :

The Impact of Communications Convergence on Silicon Integrated Circuits

Shojiro Asai

Corporate Officer and President, Research & Development Group, Hitachi Ltd., Japan

EDA Vendor Executive Panel :

Can We Rely on EDA Vendors for the Next Generation Design Technologies?

A1.1	"A VLSI Implementation of the Blowfish Encryption/Decryption Algorithm" Michael C.-J. Lin, Youn-L. Lin National Tsing Hua Univ., Taiwan
A1.2	"VLSI Implementation of Rake Receiver for IS-95 CDMA Testbed using FPGA" Oliver Y-h. Leung, Chi-Y.Tsui, Roger S. Cheng Hong Kong Univ. of Science and Technology, China
A1.3	"VLSI Implementation of a Switch Fabric for Mixed ATM and IP Traffic " Chi-Y. Tsui, Louis Chung-Y. Kwan, Chin-T. Lea Hong Kong Univ. of Science and Technology, China
A1.4	"Design of Digital Neural Cell Scheduler for Intelligent IB-ATM Switch" J.Lee, S. Lee, M.Lee, D.Lee, Y.Kim, S.Jeong Dongshin Univ., Korea
A1.5	"Genetic Algorithm Accelerator GAA-II" Shin'ichi Wakabayashi Hiroshima Univ., Japan Tetsuhi Koide Univ. of Tokyo, Japan Nayoshi Toshine, Masataka Yamane, Hajime Ueno Hiroshima Univ., Japan
A1.6	"A Programmable Buit-In Self-Test Core for Embedded Memories" Chih-T. Huang, Jing-R. Huang, Cheng-W. Wu National Tsing Hua Univ., Taiwan
A1.7	"An Algorithm for VLSI Implementation of Highly Efficient Cubic-Polynomial Evaluation" Fan Mo, Yiha Zhang, Jun Yu, Qianling Zhang Fudan Univ., China
A1.8	"Design of Self-timed Asynchronous Booth's multiplier" Tin-Y. Tang, Chin-S. Choy, Pui-L. Siu, Cheong-F. Chan The Chinese Univ. of Hong Kong, China
A1.9	"High Speed and Ultra-Low Power 16x16 MAC Design using TG for Web-based Multimedia System" Seung-M. Lee, Jin-H. Chung, Hying-S. Yoon, Mike M-O. Lee Dongshin Univ., Korea
A1.10	"A Smart Imager for the Vision Processing Front-END" Naoki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata Hiroshima Univ., Japan
A1.11	"A Bunary Image Sensor with Flexible Motion Vector Detection using Block Matching Method" Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada Univ. of Tokyo, Japan
A1.12	"An Arbitrary Chaos Generator Core Circuit Using PWM/PPM Signals" Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atushi Iwata Hiroshima Univ., Japan
A1.13	"An Application Specific Java Processor with Reconfigurablities" Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe Nara Inst. of Science and Technology, Japan
A1.14	"Reconfigurable Synchoronized Dataflow Processor" Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura Tohoku Univ., Japan
A1.15	"Prototype Microprocessor LSI with Scheduling Support Hardware for Operating System on Multiprocessor System" Naoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka Hiroshima City Univ., Japan
A1.16	"A Floating Point Arithmetic Unit for a Static Scheduling and Compiler Oriented Multiprocessor System ASCA" Takahiro Kawaguti, Takayuki Suzuki, Hideharu Amano Keio Univ., Japan
A1.17	"A 16bit redundant binary multiplier using low-power pass-transistor logic SPL" Hirofumi Sakamoto Hiroshima City Univ., Japan Ken'ichiro Uda, Bu-Y. Lee Kobe Univ., Japan Hiroyuki Ochi Hiroshima City Univ., Japan Kazuo Taki Kobe Univ., Japan Takao Tsuda Hiroshima City Univ., Japan
A1.18	"An 8x8 nRERL Serial Multiplier for Ultra-Low-Power Applications" Joonho Lim, Dong-G. Kim, Sang-C. Kang, Soo-I. Chae Seoul National Unv., Korea

B1.1	Embedded Tutorial : "Essential Issues for IP Reuse" Daniel D. Gajski Univ. of California, Irvine, USA Viraphol Chaiyakul Y Explorations Inc., USA Allen C.-H. Wu Tsing Hua University, Taiwan Shojiro Mori Toshiba Corp., Japan Tom Nukiyama NEC Corp., Japan Larry Rosenberg VSIA, USA
B1.2	"Usage-Based Characterization of Complex Functional Blocks for Reuse in Behavioral Synthesis" Nong Fan, Viraphol Chaiyakul Y Explorations, Inc., USA Daniel D. Gajski Univ. of California, Irvine, USA
B1.3	"Reuse and Protection of Intellectual Property in the SpecC System" Rainer Doemer, Daniel D. Gajski Univ. of California, Irvine, USA
B1.4	"Fair Watermarking Techniques" Gang Qu, Jennifer L. Wong, Miodrag Potkonjak Univ. of California, Los Angeles, USA

C1.1	"An Efficient Heuristic for State Encoding Minimizing the BDD Representations of the Transition Relations of Finite State Machines" Riccardo Forth, Paul Molitor Univ. Halle-Wittenberg, Germany
C1.2	"Automatic Partitioning for Efficient Combinational Verification" Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita Fujitsu Labs. of America, USA
C1.3	"A Hardware Simulation Engine Based on Decision Diagrams" (Short Paper) Yukihiro Iguchi Meiji Univ., Japan Tsutomu Sasao, Munehiro Matsuura Kyushu Inst. of Technology, Japan Atsumu Iseno Meiji Univ., Japan
C1.4	"Formal Verification based on Assume and Guarantee Approach - A Case Study" (Short Paper) Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata Fujitsu Laboratories Ltd., Japan
C1.5	"Multi-Clock Path Analysis Using Propositional Satisfiability" Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe Nara Inst. of Science and Technology, Japan

D1.1	"Self-Reforming Routing for Stochastic Search in VLSI Interconnection Layout" Yukiko Kubo Tokyo Inst. of Technology, Japan Yasuhiro Takashima Japan Advanced Inst. of Science and Technology, Japan Shigetoshi Nakatake Kitakyushu Univ., Japan Yoji Kajitani Tokyo Inst. of Technology, Japan
D1.2	"An Interconnect Topology Optimization by a Tree Transformation" Naofumi Tsujii Chuo University, Japan Katsutoshi Baba Fujitsu Corp., Japan Shuji Tsukiyama Chuo University, Japan
D1.3	"Timing-Driven Hierarchical Global Routing with Wire-Sizing and Buffer-Insertion for VLSI with Multi-Routing-Layer" Takahiro Deguchi Hiroshima Univ., Japan Tetsushi Koide Univ. of Tokyo, Japan Shin'ichi Wakabayashi Hiroshima Univ., Japan
D1.4	"Area Routing Oriented Hierarchical Corner Stitching with Partial Bin" Zhang Yan, Wang Baohua, Cai Yici, Hong Xianlong Tsinghua Univ., China

A2.1	"Offline Program Re-mapping to Improve Branch Prediction Efficiency in Embedded Systems" Stephen S. Brown, Jeet Asher, William H. Mangione-Smith Univ. of California, Los Angeles, USA
A2.2	"Timing Driven Co-design of Networked Embedded Systems" Dinesh Ramanathan, Ravindra Jejurikar, Rajesh K. Gupta Univ. of California, Irvine, USA
A2.3	"Low-power Design Methodology and Applications utilizing Dual Supply Voltages" Kimiyoshi Usami, Mutsunori Igarashi Toshiba Corp., Japan
A2.4	"Co-Synthesis with custom ASICs" Yuan Xie, Wayne Wolf Princeton University, USA

B2.1	"A New Method for Constructing IP Level Power Model Based on Power Sensitivity" Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou National Chiao-Tung Univ., Taiwan
B2.2	"A hybrid approach for core-based system-level power modeling" Tony Givargis, Frank Vahid Univ. California, Riverside, USA Joerg Henkel NEC USA
B2.3	"Voltage Reduction of Application-Specific Heterogeneous Multiprocessor Systems for Power Minimisation" Allan Rae, Sri Parameswaran The Univ. of Queensland, Australia
B2.4	"Withdrawn"
B2.5	"Synthesis of Low Power Folded Programmable Coefficient FIR Digital Filters" (Short Paper) Vijay Sundararajan, Keshab K. Parhi Univ. of Minnesota, USA

C2.1	Invited Talk : "Synthesis Challenges for Next-Generation High-Performance and High-Density PLDs" Jason Cong Univ. of California, Los Angeles, USA Songjie Xu Aplus Design Technologies, Inc., USA
C2.2	"KressArray Xplorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures" Reiner Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger Univ. of Kaiserslautern, Germany
C2.3	"Hardware-Software Cosynthesis for Run-time Incrementally Reconfigurable FPGAs" Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi Seoul National Univ., Korea

D2.1	"A New Encoding Scheme for Rectangle Packing Problem" Toshihiko Takahashi Niigata Univ., Japan
D2.2	"Analytical Minimization of Half-Perimeter Wirelength" Andrew A. Kennings Univ. of Waterloo, Canada Igor L. Markov Univ. of California, Los Angeles, USA
D2.3	"Modeling and Minimization of Routing Congestion" Maogang Wang, Majid Sarrafzadeh Northwestern University, USA

E2.1	"System-In-Package (SIP) : Challenges and Opportunities" King L. Tai Bell Laboratories, Lucent Technologies, USA
E2.2	"Taiwan Foundary for System-In-Package (SIP)" Albert Lin APack, Inc., Taiwan
E2.3	"Integration of Large-Scale FPGA and DRAM in a Package Using Chip-On-Chip Technology" Michael X. Wang, Katsuharu Suzuki, Wayne W.-M. Dai Univ. of California, Santa Cruz, USA Yee L. Low, Kevin J. O'conner, King L. Tai Bell Laboratories, Lucent Technology, USA
E2.4	"Modeling and Analysis of Integrated Spiral Inductors for RF System-In-Package (SIP)" Minqing Liu, Wayne W.-M. Dai Univ. of California, Santa Cruz, USA

Keynote Address II :

Research, Design, and Fabrication - Brain Power, Tool Power, and Electric Power

C. L. Liu

President, National Tsing Hua Univ., Hsin-Chu, Taiwan

A3.1	"Narrow Bus Encoding for Low Power Systems" Youngsoo Shin, Kiyoung Choi Seoul National Univ., Korea
A3.2	"Data Transmission over a Bus with Peak-Limited Transition Activity" Vijay Sundararajan, Keshab K. Parhi Univ. of Minnesota, USA
A3.3	"Power Analysis and Implementation of a Low-Power 300 MHz 8-b x 8-b Pipelined Multiplier" Jinn-Shyan Wang, Po-Hui Yang National Chung Cheng University, Taiwan

B3.1	"A New Approach to Assembly Software Retargeting for Microcontrollers" Ing-Jer Huang, Dao-Zhen Chen National Sun Yat-sen Univ., Taiwan
B3.2	"Register Allocation for Common Subexpressions in DSP Data Paths" Rainer Leupers Univ. of Dortmund, Germany
B3.3	"A Technique for QoS-based System Partitioning" Johnson S. Kin, Chunho Lee, William H. Mangione-Smith, Miodrag Potkonjak Univ. of California, Los Angeles, USA

C3.1	"Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions" Debatosh Debnath, Tsutomu Sasao Kyushu Inst. of Technology, Japan
C3.2	"An Efficient Framework of Using Various Decomposition Methods to Synthesize LUT Networks and Its Evaluation" Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya NTT Communication Science Laboratories, Japan
C3.3	"Three Parameters to Find Functional Decompositions" Tsutomu Sasao, Ken-ichi Kurimoto Kyushu Inst. of Technology, Japan

D3.1	"Delay-Optimal Wiring Plan for the Microprocessor of High Performance Computing Machines" Jun Kikuchi, Tetsuo Sasaki Hitachi, Ltd., Japan Tohru Hashimoto Hitachi Information Technology Co., Ltd., Japan Kazuhisa Miyamoto Hitachi, Ltd., Japan
D3.2	"MMP : A Novel Placement Algorithm for Combined Macro Block and Standard Cell Layout Design" Hong Yu, Xianlong Hong, Yici Cai Tsinghua Univ., China
D3.3	"Dynamic Weighting Monte Carlo for Constrained Floorplan Designs in Mixed Signal Application" Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang Univ. of California, Los Angeles, USA Jun S. Liu Stanford Univ., USA Wing Hung Wong Univ. of California, Los Angeles, USA

E3.1	"Symbolic Circuit-Noise Analysis and Modeling with Determinant Decision Diagrams" XiangDong Tan, C.-J. Richard Shi Univ. of Washington, USA
E3.2	"Gate-Level Aged Timing Simulation Methodology for Hot-Carrier Reliability Assurance" Yoshiyuki Kawakami Matsushita Electrical Industrial, Co. Ltd., Japan Jingkun Fang BTA Technology Inc., USA Hirokazu Yonezawa, Nobufusa Iwanishi Matsushita Electrical Industrial, Co. Ltd., Japan Lifeng Wu, Alvin I-Hsien Chen BTA Technology Inc., USA Norio Koike Matsushita Electronics Corp., Japan Ping Chen, Chune-Sin Yeh, Zhihong Liu BTA Technology Inc., USA
E3.3	Embedded Tutorial : "Subwavelength Lithography Technologies (PSM, OPC)" Tsuneo Terasawa Hitachi Ltd., Japan

A4.1	Embedded Tutorial : "IC Design Technology for Building System-On-A-Chip" Rajesh Gupta Univ. of California, Irvine, USA
A4.2	"Thread Partitioning Method for Hardware Compiler Bach" Mizuki Takahashi Sharp Corp., Osaka Univ., Japan Nagisa Ishiura Osaka Univ., Japan Akihisa Yamada, Takashi Kambe Sharp Corp., Japan
A4.3	"An Area/Time Optimizing Algorithm in High-Level Synthesis for Control-Based Hardwares" (Short Paper) Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki Waseda Univ., Japan
A4.4	"A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders" (Short Paper) Taewhan Kim, Junhyung Um Korea Advanced Inst. of Science and Technology, Korea

B4.1	"Communicating Logic : An Alternative Embedded Stream Processing Paradigm" Norbert Imlig, Ryusuke Konishi, Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Minoru Inamori, Hiroshi Nakada NTT Network Innovation Laboratories, Japan
B4.2	"A Scheduling and Allocation Method to Reduce Data Transfer Time by Dynamic Reconfiguration" Kazuhito Ito Saitama Univ., Japan
B4.3	Invited Talk : "Reconfigurable Computing: Its Concept and a Practical Embodiment using Newly Developed Dynamically Reconfigurable Logic (DRL) LSI" Masakazu Yamashina, Masato Motomura NEC Corp., Japan

C4.1	"Power Reduction by Simultaneous Voltage Scaling and Gate Sizing" Chunhong Chen, Majid Sarrafzadeh Northwestern Univ., USA
C4.2	"Analysis of Power-Clocked CMOS with Application to the Design of Energy-Recovery Circuits" Massoud Pedram Univ. of Southern California, USA Xunwei Wu Zhejiang Univ., China
C4.3	"Low-Power Design of Sequential Circuits Using a Quasi-Synchronous Derived Clock" Xunwei Wu, Jian Wei Zhejian Univ., China Massoud Pedram, Qing Wu Univ. of Southern California, USA
C4.4	"FSM Decomposition by Direct Circuit Manipulation Applied to Low Power Design" Jose C. Monteiro, Arlindo L. Oliveira IST-INESC, Portugal

E4.1	"High Performance of Short-Channel MOSFETs due to an Elevated Central-Channel Doping" M. Tanaka, N. Tokida, T. Okagaki, M. Miura-Mattausch, W. Hansch, H. J. Mattausch Hiroshima Univ., Japan
E4.2	"Circuit Performance Oriented Device Optimization using BSIM3 Pre-Silicon Model Parameters" Mikako Miyama, Shiro Kamohara Hitachi Ltd, Japan
E4.3	Embedded Tutorial : "Design for Manufacturability" Andrzej J. Strojwas Carnegie Mellon Univ., USA

A5.1	Embedded Tutorial : "Low-Power Silicon Architectures for Wireless Communications" Jan Rabaey Univ. of California, Berkeley, USA
A5.2	"Run-time Power Control Scheme using Software Feedback Loop for Low-power Real-time Application" Seongsoo Lee, Takayasu Sakurai Univ. of Tokyo, Japan
A5.3	"An Interleaved Dual-Battery Power Supply for Battery-Operated Electronics" Qing Wu, Qinru Qiu, Massoud Pedram Univ. of Southern California, USA

B5.1	Embedded Tutorial : "Multilanguage System Design" Rolf Ernst Technical University Braunschweig, Germany Ahmed A. Jerraya TIMA Laboratory, France
B5.2	"Symbolic Debugging of Globally Behavioral Specifications" Darko Kirovski, Inki Hong, Miodrag Potkonjak Univ. of California, Los Angeles, USA Marios C. Papaefthymiou Univ. of Michigan, USA
B5.3	"Fast Development of Source-level Debugging System Using Hardware Emulation" (Short Paper) Sang-Joon Nam, Jun-Hee Lee, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Kyong-Gu Kang, Chong-Min Kyung Korea Advanced Inst. of Science and Technology, Korea
B5.4	"Methodology for Hardware/Software Co-verification in C/C++" (Short Paper) Luc Semeria Stanford Univ., USA Abhijit Ghosh Synopsys Inc., USA

C5.1	"Performance-Optimal Clustering with Retiming for Sequential Circuits" Tzu-Chieh Tien, Youn-Long Lin Tsing Hua Univ., Taiwan
C5.2	"IBAW: An Implication-Tree Based Alternative-Wiring Logic Transformation Algorithm" Wangning Long Tsinghua Univ., China Yu-Liang Wu The Chinese Univ. of Hong Kong, China Jinian Bian Tsinghua Univ., China
C5.3	"On Mixture Density and Maximum Likelihood Power Estimation via Expectation-Maximization" R. Chandramouli Iowa State Univ., USA Vamsi K. Srikantam Hewlett Packard Labs, USA

D5.1	"Edge Seperability Based Circuit Clustering with Application to Circuit Partitioning" Jason Cong, Sung Kyu Lim Univ. of California, Los Angeles, USA
D5.2	"Feasible Two-Way Circuit Partitioning with Complex Resource Constraints" Hsun-Cheng Lee, Ting-Chi Wang Chung Yuan Christian Univ., Taiwan
D5.3	"Performance Driven Multiway Partitioning" Jason Cong, Sung Kyu Lim Univ. of California, Los Angeles, USA

E5.1	"Hierarchical Computation of 3-D Interconnect Capacitance using Direct Boundary Element Method" Jiangchun Gu, Zeyi Wang, Xianlong Hong Tsinghua Univ., China
E5.2	"A Simplified Hybrid Method for Calculating the Frequency-dependent Inductances of Transmission Lines with Rectangular Cross Section" Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong Tsinghua Univ., China
E5.3	"An Analytic Calculation Method for Delay Time of RC-class Interconnects" W. K. Kal, S. Y. Kim SoongSil Univ., Korea
E5.4	"A New Efficient Waveform Simulation Method for RLC Interconnect via Amplitude and Phase Approximation" Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng University of California, San Diego, USA

Keynote Address III :

Design Challenges in Multi-GHz Microprocessors

Bill Herrick

Director, Alpha Microprocessor Development, Compaq Computer Corp., USA

A6.1	"Optimization of VDD and VTH for Low-Power and High Speed Applications" Koichi Nose, Takayasu Sakurai Univ. of Tokyo, Japan
A6.2	"Compact yet High Performance (CyHP) Library for Short Time-to-Market with New Technologies" Nguyen Minh Duc, Takayasu Sakurai Univ. of Tokyo, Japan
A6.3	"A New CMAC Neural Network Architecture and Its ASIC Realization" Yuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang Chung-Cheng Univ., Taiwan

B6.1	"Retargetable Estimation Scheme for DSP Architecture Selection" Naji Ghazal, Richard Newton, Jan Rabaey Univ. of California, Berkeley, USA
B6.2	"Data Memory Minimization by Sharing Large Size Buffers" Hyunok Oh, Soonhoi Ha Seoul National Univ., Korea
B6.3	"Array Allocation Taking into Account SDRAM Characteristics" Hong-Kai Chang, Youn-Long Lin Tsing Hua Univ., Taiwan

C6.1	"Causality Based Generation Of Directed Test Cases" Nina Saxena Intel Corp., USA Jacob Abraham Univ. of Texas, Austin, USA Avijit Saha IBM Austin, USA
C6.2	Embedded Tutorial : "Fault models and test generation for IDDQ Testing" Yoshinobu Higami Ehime Univ., Japan Kewal K. Saluja Univ. of Wisconsin Yuzo Takamatsu Ehime Univ., Japan Kozo Kinoshita Osaka Univ., Japan
C6.3	Embedded Tutorial : "Issues on SOC Testing in DSM Era" Takashi Aikyo Fujitsu Ltd., Japan

D6.1	"A Cell Synthesis Method for Salicide Process" Kazuhisa Okada, Takayuki Yamanouchi, Takashi Kambe Sharp Corp., Japan
D6.2	"Monte-Carlo Algorithms for Layout Density Control" Yu Chen, Andrew B. Kahng Univ. of California, Los Angeles, USA Gabriel Robins Univ. of Virginia, USA Alex Zelikovsky Geogia State Univ., USA
D6.3	"Layout Generation of Array Cell for NMOS 4-phase Dynamic Logic" (Short Paper) Makoto Furuie, Bao-Yu Song, Yukihiro Yoshida, Takao Onoye, Isao Shirakawa Osaka Univ., Japan
D6.4	"A New Efficient Method for Substrate-Aware Device-Level Placement" (Short Paper) C. Lin Eindhoven Univ. of Technology, The Netherlands D. M. W. Leenaerts Philips Research Labs., The Netherlands

E6.1	"The Enhancing of Efficiency of the Harmonic Balance Analysis by Adaptation of Preconditioner to Circuit Nonlinearity" M. M. Gourary, S. G. Rusakov, S. L.. Ulyanov, M. M. Zharov IPPM, Russian Academy of Science, Russia K. K. Gullapalli, B. J. Mulvaney Motorola, USA
E6.2	"Analog-Testability Analysis by Determinant-Decision-Diagrams based Symbolic Analysis" Tao Pi, C.-J. Richard Shi Univ. of Washington, USA
E6.3	"A Method for Linking Process-level Variability to System Performances" Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru Kyoto Univ., Japan

A7.1	Embedded Tutorial : "Design Challenges for 0.1um and Beyond" Takayasu Sakurai Univ. of Tokyo, Japan
A7.2	"A Hardware Accelerator for the Specular Intensity of Phong Illumination Model in 3-Dimensional Graphics" Young-Su Kwon, In-Cheol Park, Chong-Min Kyung Korea Advanced Inst. of Science and Technology, Korea
A7.3	"Radix-4 Modular Multiplication and Exponentiation Algorithms for the RSA Public-Key Cryptosystem" Jin-Hua Hong, Cheng-Wen Wu Tsing Hua Univ., Taiwan

B7.1	"SLDL and Rosetta" Steven Schulz Texas Instruments, Inc., USA
B7.2	"SystemC Standard" Guido Arnout Co-Ware, Inc., USA
B7.3	"Java based object oriented hardware specification and synthesis" Tommy Kuhn, Wolfgang Rosenstiel Univ. of Tuebingen, Germany
B7.4	"Superlog, A Unified Design Language for System-on-chip" Peter Flake, Simon J. Davidmann Co-Design Automation, Inc., USA

C7.1	"Performance Sensitivity Analysis Using Statistical Method and Its Applications to Delay Testing" Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng Univ. of California, Santa Barbara, USA Deb Aditya Mukherjee, Sandip Kundu Intel Corp., USA
C7.2	"A Testability Metric for Path Delay Faults and Its Application" Huan-Chih Tsai, Kwang-Ting Cheng Univ. of California, Santa Barbara, USA Vishwani D. Agrawal Bell Laboratories, Lucent Technologies, USA
C7.3	"A Non-Scan DFT Method at Register-Transfer Level to Achieve Complete Fault Efficiency" Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara Nara Inst. of Science and Technology, Japan
C7.4	"A Sigma-Delta Modulation Based BIST Scheme for Mixed-Signal Circuits" Jiun-Lang Huang, Kwang-Ting Cheng Univ. of California, Santa Barbara, USA

E7.1	"A 12b 50 MHz 3.3V CMOS Acquisition Time Minimized A/D Converter" Young-Deuk Jeon Sogang Univ., Korea Byeong-Lyeol Jeon Hundai Electronics Industries Co., Ltd, Korea Seung-Chul Lee, Sang-Min Yoo, Seung-Hoon Lee Sogang Univ., Korea
E7.2	"A Benchmark Suite for Substrate Analysis" Edoardo Charbon Cadence Design Systems, Inc., USA Luis Miguel Silveira INESC, Portugal Paolo Miliozzi Conxant Systems, Inc., USA
E7.3	Embedded Tutorial : "Substrate Crosstalk Analysis in Mixed Signal CMOS Integrated Circuits" Makoto Nagata, Atsushi Iwata Hiroshima Univ., Japan

A8.1	Invited Talk : "Importance of CAD Tools and Methodology in High Speed CPU Design" Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu Toshiba Corp., Japan Yasuyuki Yamamoto, Masakazu Suzuoki Sony Computer Entertainment, Japan
A8.2	"300MHz design methodology of VU for Emotion Synthesis" Takayuki Kamei, Hideki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu Toshiba Corp., Japan
A8.3	"Repeater Insertion Method and its application to a 300MHz 128-bit 2-way Superscalar Microprocessor" Norman Kojima Toshiba Corp., Japan Yukiko Parameswar, Christian Klingner Toshiba America Electronic Components, Inc., USA Yukio Ohtaguro, Masataka Matsui, Shigeaki Iwasa, Tatsuo Teruyama, Takayoshi Shimazawa, Hideki Takeda Toshiba Corp., Japan Kouji Hashizume Toshiba Microelectronics Corp., Japan Haruyuki Tago, Masaaki Yamada Toshiba Corp., Japan
A8.4	"Clock Design of 300MHz 128-bit 2-way Superscalar Microprocessor" Fujio Ishihara Toshiba Corp., Japan Christian Klingner Toshiba America Electronic Components, Inc., USA Ken-ichi Agawa Toshiba Corp., Japan

D8.1	"Circuit Partitioning with Coupled Logic Restructuring Techniques" Yu-Liang Wu The Chinese Univ. of Hong Kong, China Xiao-Long Yuan The Northwest Polytechnical Univ., China David Ihsin Cheng Ultima Interconnect Technology, USA
D8.2	"Improved Algorithms for Hypergraph Bipartitioning" Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov Univ. of California, Los Angeles, USA
D8.3	"Multi-way Partitioning Using Bi-partition Heuristics" Maogang Wang Northwestern Univ., USA Sung Lim, Jason Cong Univ. of California, Los Angeles, USA Majid Sarrafzadeh Northwestern Univ., USA