| Tutorials |
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Full-Day Tutorials (Tuesday, January 25, 9:30-17:00)
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| Tutorial 1: Hardware/Software Techniques for Embedded Microprocessor/Microcontroller Design and Applications |
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Organizer:
Ing-Jer Huang - National Sun Yat-Sen Univ., Taiwan
Microprocessors/microcontrollers have been widely used and studied in both academies and industries for decades. However, their design processes and application practices are now facing a new challenge: the trend of SoC (system-on-chip) chips has redefined the characteristics of microprocessors/microcontrollers from standard, stand-along and general-purpose products to customizable, embedded and application-specific ones. The objective of this tutorial is to investigate issues related to the new challenges from three aspects: hardware design, software development and CAD techniques.
9:30-10:50
Design of the reusable 8-bit W65C02
microcontroller family
11:10-12:30 Design of the reusable 32-bit ARM
microprocessor family
The first topic addresses the problems in the development of reusable (or IP, intellectual property) microprocessor/ microcontroller cores and approaches to solve the problems. The topic is covered by two presentations, one in the 8-bit microcontroller area by Mr. William D. Mensch, Jr. and Mr. Lars H. Dannemann, and one in the 32-bit microprocessor area by Mr. Simon Segars. Mr. Mensch is the founder, chairman and CEO of the Western Design Center (WDC), a successful provider of the 6502 related microcontroller cores. He has numerous patents for microprocessors, microprocessor peripheral devices and microprocessor systems, and was recognized in both 1991 and 1996 at the Microprocessor Forum as a pioneer in the microprocessor industry. Mr. Dannemann is the Engineering Manager at WDC, responsible for soft core design and hardware/software design of development systems. Mr. Segars manages ARM's CPU Development Group in Cambridge, UK. He was the project manager and technical lead of the ARM7TDMI project, currently the company's highest volume shipping product. He also ran the ARM9TDMI and ARM940T projects and most recently has overseen the evolution of the ARM9 family into soft-IP.
14:00 - 15:20
Retargeting and Reverse Engineering of
binary code The second topic covers the machine code retargeting problem whichhappens when a system designer hope to switch to a new microprocessor/microcontroller with better performance/cost/flexibility but hindered by existing software which has been developed on legacy instruction sets. This topic is covered by Professor Cristina Cifuentes. She is the leader of the Binary group within the Centre for Software Maintenance, which researches techniques in the areas of binary translation and reverse engineering of binary code, including semantic analysis for the recovery of abstract information from low level binary code, and machine-independent analyses. That work is funded by an ARC large grant and internationally from Sun Microsystems.
15:40 - 17:00
Design and CAD Techniques The third topic presents CAD techniques to solve the design anddevelopment problems of microcontrollers. The CAD techniques are selected or developed under the requirement that they are simple to be comprehended and implemented, yet sufficient enough to solve real industry problems effectively. This topic is covered by Professor Ing-Jer Huang. He has researched in the areas of microprocessor design and design automation for more than ten years. Many of his techniques have been successfully applied to the design of industrial microprocessors, such as Teledyne's TDY-43, Holtek's HT48x00, and x86 compatible processors. He also serves as a consultant to IC companies. Recommended Audiences: The targeted audiences include researchers, students, engineers and managers involving the design and application of microprocessor/microcontroller cores, embedded system design, embedded software, and related CAD development. |
| Tutorial 2: Power Reduction Techniques for Portable DSP Applications |
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Organizer:
Mahesh Mehendale - Texas Instruments Ltd., India
While general purpose computation specifies a "do-the-best-you-can" metric to the designer, Digital Signal Processing (DSP) is characterized by an optimization problem with a given throughput requirement. This tutorial will concentrate on power reduction techniques specific to DSP. Coverage will range from circuit design to program optimization with power dissipation as the metric. In particular, the circuit design techniques will focus on asynchronous design methodologies.
9:30 - 10:50
Introduction In this session we will first characterize the computation problem of signal processing and distinguish it from general-purpose computation. We will then state the problem of power reduction and highlight its importance. Finally, the session will cover an outline of power reduction techniques and classify them into circuit-level, logic-level, architecture-level, algorithmic-level and system-level techniques.
11:10 - 12:30 Programmable DSP Based
Implementation In this session we will first cover the salient features of programmable DSP architectures that enable efficient implementation of weighted-sum based DSP kernels such as FIR filters. We will identify the sources and measures of power dissipation and present various algorithmic and architectural transformations to power reduction. The session will also look at low power code generation of multiplication-free linear transforms. Finally, the session will present low power architectural extensions to programmable DSPs.
14:00 - 15:20
Hardwired Implementation In this session we will present power reduction techniques for hardwired implementation of weighted-sum based DSP kernels. The focus will be on algorithmic and architectural transformations to minimize power dissipation for the following implementation styles:
15:40 - 17:00
Trends and Challenges In this session we will first explain how the opportunity for dynamic power management arises from the variation in throughput requirement of a system. We then describe the techniques for dynamically adjusting power levels through voltage and clock frequency scaling techniques. We will then review various techniques for asynchronous circuit design such as QDI and micro-pipelines, and bring out the intrinsic advantages of these techniques over synchronous design w.r.t. power dissipation. We will conclude the session with a discussion on challenges for the future and corresponding research opportunities.
Recommended Audiences: |
| Tutorial 3: Test Techniques for Heterogeneous System-on-Chip Devices |
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Organizer:
Cheng-Wen Wu - National Tsing-Hua Univ., Taiwan
Advances in manufacturing and design technology enable the design of complex, heterogeneous system-on-chips. Such SOCs, typically containing digital, analog and memory blocks, require more re-use of components and their tests. This one-day tutorial will cover representative test techniques for such complex ICs. Special emphasis will be given to memory testing, analog and mixed-signal testing, BIST for logic, memory and analog components, test synthesis for digital circuitry, test economics of memory and logic BIST, and IDDQ testing.
9:30-10:50
Introduction and RAM Testing In this first session, a brief introduction and outline of the entire tutorial will be given first, then we will cover the basic RAM testing topics, including SRAM and DRAM fault models, popular RAM test algorithms, testing bit-oriented memories, testing word-oriented memories, cocktail-March algorithms, fault coverage analysis, and test-algorithm optimization.
11:10-12:30
Memory BIST and Logic BIST For memory BIST, in addition to testing the memory cores by using March-based algorithms we also will discuss fault diagnosis and repair by redundant word- and/or bit-lines. For logic BIST, we will discuss techniques for random-pattern testability, scan-based BIST architectures and issues on diagnosis. Specifically, we will cover RAM BIST, RAM built-in redundancy analysis (BIRA), diagnosis in memory BIST, logic BIST pattern generator and response analyzer, scan-based BIST architecture, test point insertion for improving random testability, and diagnosis in logic BIST.
14:00-15:20
BIST Economics and Mixed-Signal
Testing Analysis of costs and benefits for BIST is definitely helpful for the project manager and designers. We will discuss the economics of BIST for logic and memory cores and economics of DFT for SOC. Since SOCs usually contain analog and mixed-signal circuitry which often dominates the design and test cost and time-to-market, DFT and BIST techniques for analog nd mixed-signal components are becoming a reality and a necessity. We will first review analog/mixed-signal DFT techniques, including IEEE P1149.4 mixed-signal test bus, then discuss principles and techniques of DSP-based BIST methods.
15:40-17:00
IDDQ Testing and New Challenges of
SOC Testing We will give an overview of IDDQ testing and also examine some issues surrounding IDDQ testing in deep-submicron devices. Finally, the tutorial will conclude with comments on the new challenges for test. The test community must cope with an enormous spectrum of difficult problems ranging from, for instance, test synthesis for core-based design to noise and power dissipation problems in extremely high performance (in reality analog) pin electronics. We will examine the test challenges posed by test equipment, design technology and semiconductor technology.
Recommended Audience: |
| Tutorial 4: Trends in Front-End Optimization and Verification Approaches to Deep-Submicron Design Closure |
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Organizer: Mike T.-C. Lee - Incentia Design
Systems, USA
With advent of deep-submicron (DSM) processing technology, VLSI front-end designers are facing two immediate challenges: achieve rapid design closure by optimization to meet DSM objectives even after layout, and verify functionality of such optimized designs with over million-gate complexity. This tutorial presents recent advance in front-end solutions to the DSM challenges with focus on formal verification, performance/power optimization, and their integration with back-end physical design flow.
9:30 - 10:50
Introduction In this session, we will discuss the general DSM issues with current design methodology, and outline the topics in our presentation that will address these issues. We will also stress the importance of considering the DSM effects at front-end design stage while performing optimization and verification.
11:10 - 12:30
Using Formal Verification in DSM
Environment DSM has been giving many new challenges to formal verification techniques. Sizes of designs to be verified are getting bigger, and there are more aggressive modifications to the circuit even after layout is done in order to meet design objectives. Also, many designs are based on collections of existing designs, i.e., IP reusable cores. We will summarize important problems related to DSM that need to be solved by formal verification techniques, and present how to apply formal verification to those problems. We will also study performance of state-of-the-art formal verification technology, and show how to improve verification performance by "intelligently using formal verification techniques."
14:00 - 15:20
Meeting Timing Requirement in DSM Era Timing closure becomes hard to guarantee by conventional design methodology where synthesis and layout are decoupled. We will present recent work on DSM timing optimization techniques that integrate synthesis and layout. We first review conventional synthesis and layout optimization methods for delay reduction. We then discuss DSM physical effects, and new solutions to timing convergence by combining RTL synthesis, logic synthesis, floorplanning, and layout.
15:40 - 17:00
Reducing Power for High-Performance
DSM Design Power consumption has become one of the biggest challenges in high-performance designs. We will discuss the main trends in low power designs, and use specific example of high-performance CPUs to show the issues that make power reduction hard in high-end designs. We will look at the techniques that have worked in real designs and point out relevant directions that need further research. We will also review keyhigh-level ideas that give the biggest return in low power design. They include dynamic power management, software power analysis and optimization, and architecture optimizations.
Recommended Audiences: |
| Tutorial 5: Ultra Deep Submicron Design and Analysis |
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Organizer: Res Saleh - Simplex Solutions, USA
This tutorial describes deep submicron design and verification challenges that have been encountered as designs move to 0.25¦Ìm and below. First, the beneficial impact of UDSM on different applications are described, followed by a discussion of new design problems created by UDSM. Next, techniques for parasitic extraction, reduction and delay calculation are described. Then, power grid verification for IR drop and long-term reliability is presented. Finally, issues of signal integrity in terms of capacitive coupling and inductive effects are described.
9:30 - 10:50
Overview of UDSM Design Challenges Ultra deep submicron technology has provided extremely high levels of integration and made system-on-a-chip feasible. Almost every application has benefited from DSM including microprocessors, memory, graphics processors, digital signal processors, and network chips, to name a few. Line widths of 0.25¦Ìm and 0.18¦Ìm with 6-7 layers of metal are now in production. However, as the geometries shrink, design complexity also increases due to UDSM effects. This tutorial describes the key issues in DSM design and some of the new technologies being introduced such as copper, low-K dielectrics and silicon-on-insulator substrates.
11:10 - 12:30
Parasitic Extraction and Delay
Calculation One of the key issues in DSM technology is the dominance of interconnect delay over the gate delay. The parasitics associated with interconnect play a vital role in the overall chip timing to the point where timing convergence has been difficult to achieve in the place-and-route loop. The use of the RC parasitic information in delay analysis for timing verification becomes more challenging when taking into account coupling for 0.25 ¦Ìm, process variation for 0.18 um, and on-chip inductance for 0.13 ¦Ìm. This tutorial will survey full chip 3D parasitic extraction approaches and integrated delay analysis solutions.
14:00 - 15:20
IR drop and Reliability in UDSM Power distribution verification has become a necessary step in UDSM design of integrated circuits. With the increased loads and reduced voltages of UDSM circuits, more failures have occurred due to poorly designed power distribution systems. Failures were initially observed in microprocessor designs, but are now common in ASSP and ASIC design. With the narrow noise margins of a UDSM design, IR drop due to missing vias or an inadequate power grid causes functional failures, changes circuit timing and increases clock skew. Narrow line widths in UDSM have also created electromigration problems for both power and signal lines. This tutorial addresses the IR and EM issues in Al and looks ahead at the prospects for Cu.
15:40 - 17:00
Signal Integrity in UDSM Technology trends have made noise an important issue for UDSM designs. In particular, faster on-chip slew rates and increasing line-to-line coupling are producing significant increases in on-chip noise. At the same time, the noise immunity of circuits is generally being sacrificed to improve performance or reduce power. In this part of the tutorial, we consider tools and techniques for analyzing the effects of noise on the delay and functionality of UDSM designs. We also consider inductive effects which are becoming more significant with increasing on-chip frequencies.
Recommended Audiences: |