Recommended Audiences :

Designers of both hardware and software based DSP systems, developers of IP modules for DSP applications, EDA tools developers, researchers and managers interested in getting a comprehensive overview of current trends and future challenges in low power implementations of portable DSP applications.

Organizers:
Jason Cong - Univ. of California, Los Angels, USA
Patrick Groeneveld - Magma Design Automation Inc., USA

Achieving timing closure between synthesis and layout has become the biggest challenge in deep submicron chip design. The increasing significance of interconnect delay is forcing a significant re-assessment of the traditional division between the logical design and physical design steps. How can we bond logic synthesis with placement and routing such that the resulting chip will meet the original circuit timing specifications? This tutorial will provide the latest answers to this question. An in-depth technical overview of all techniques for timing closure will be discussed: new synthesis techniques, wire buffering for optimum speed, timing analysis and clocking strategies, signal integrity, etc. Also, the technical core of a number of new design systems will be presented, each operating in fundamentally different ways. The audience will be offered a strong insight in the fundamental technical problems, their solutions and the practical implications of the new methodologies.

9:30 - 10:50

An in-depth review of the existing techniques for timing closure will be presented. These techniques are used today for the design of high-performance UDSM chips. The speaker will present the full set of methods for timing correction, including buffering and manipulating wire load models. Furthermore timing analysis techniques will be presented, as well as clocking methodologies for large-scale circuit design.

11:10 - 12:30

The new 'gain-based synthesis' method will be presented in depth. The method is based on the theory of logical effort. This method essentially fixes the gate delays before physical design, rather than the gate sizes. The theory behind this new model will be derived in great detail. The presentation will describe how delay can be kept constant during placement and routing and, with that, how the timing closure can be achieved. Various practical details of this method that emerged during commercial application will also be discussed.

14:00 - 15:20

A different methodology for timing closure will be presented. It is based on simultaneous optimization and model refinement. The placement, synthesis, timing, and routing engines suitable for this 'spiraling convergence' technique will be presented, together with the framework that enables their interaction.

15:40 - 17:00

The latest developments on global interconnect planning and optimization at the chip-level will be presented in the final presentation. Buffer block planning and wire width planning can maximize the speed of the long wires crossing the chip. New methods to automate this process will be presented, together with more advanced methods for interconnect-centric designs, including floorplanning with interconnect planning, combining partitioning with retiming, etc.

Recommended Audiences :

Logic designers, layout designers and CAD engineers would benefit from understanding new algorithm and tool capabilities for achieving timing closure between synthesis and layout. This tutorial will also help design project managers and academic researchers in understanding the state-of-art the solutions for timing closure and future research directions.

Organizer: Youn-Long Lin - National Tsing Hua Univ., Taiwan

Ever increasing requirement on functionality, cost effectiveness and energy efficiency calls for electronic systems to be integrated on a single chip (system-on-a-chip, SOC). SOC designers need advanced methodology, tools, and components (silicon intellectual properties, IP) to meet their challenge. IP authoring for reuse in SOC is much different from traditional IC design. SOC integration, verification and testing must take into account many previously un-countered issues. This tutorial features four leading experts from both academia and industry. Not only advanced methodology but also practical experience will be presented.

9:30 - 10:30

The tutorial introduces several emerging SOC design methodologies with emphasis on platform-based SOC design. Topics include design methodology and reuse evolution, linking the platform-based approach to hardware/software co-design, essential design flows and tools to support this approach, hardware design of the platform and derivatives, major issues of incorporating mixed-signal blocks into SOC, and implications for embedded software and co-verification.

11:10 - 12:30

This part of the tutorial presents a Reusable IP Authoring Guideline that has been practiced by several IP vendors. Practice of these guidelines and rules leads to robust high-quality IPs for easy SOC integration. Topics will include system-level planning, disciplined coding styles, thorough verification, Design-for-Test concerns, socketization for SoC integration, and complete deliverables. Experience with the development of a DSP core will be described.

14:00 - 15:20

The third part of the tutorial will present state-of-the-art techniques for IP qualification. Several popular functional coverage metrics are surveyed and three approaches for coverage measurement are introduced. Techniques for automatic test-bench generation are also presented. These new approaches allow us to obtain high coverage without excessive simulation.

15:40 - 17:00

The final part of the tutorial describes recent development in SOC testing. After discussion of SOC test issues, requirements, and process, test methodologies for digital, memory, and analog cores will be presented. Built-in self-test techniques for the cores will be stressed. The emerging IEEE P1500 standard for SOC testing will then be presented. The P1500 Wrapper architecture and test access mechanisms will be explained. Examples for testability design at the SOC level will also be shown.

Recommended Audiences :

This tutorial is intended for IP authors and users, SOC designers, and EDA developers.

Organizer: Rajesh K. Gupta - Univ. of California, Irvine, USA

This tutorial is about design of single-chip systems characterized by a (wireline and/or wireless) network connection. Such an "antenna-to-network" chip would incorporate a RF front end, baseband digital signal processing, link layer coding and medium access control functions. The goal of this tutorial is to present a systems perspective of design, prototyping and verification of networked SOCs in the specific context of Bluetooth devices. The tutorial consists of four parts: (a) system and architectural issues for networked SOCs; (b) case studies in networked system-chip design; (c) power management for networked SOCs; (d) advances in conceptualization, modeling and simulation of networked SOCs.

9:30 - 10:50

(10:50 - 11:10 Coffee Break)

11:10 - 12:30

A major challenge in the design of single-chip solutions for wireless networked system lies in meeting the system performance with the lowest area, cost, and power. However, there exists a gap between the system engineering and integrated circuits implementation that has limited the degree of optimization one could do from the system level down to circuits implementation. This part of the tutorial focuses on top-down design approaches and techniques that help to bridge this gap. In particular, we consider system and architectural issues that are specific to the design of single-chip wireless systems. These include the choice of RF front-end architectures, modulations, error control/coding, multiple access, duplexing, and diversity combining. In Part II of this talk, several case studies will be discussed, such as the design of spread-spectrum cordless transceivers and Bluetooth radios.

14:00 - 15:20

Accurate modeling of power needs and its judicious management is critical to a good SOC design. In this talk we explore various levels of power management schemes and how coordinated approaches are being explored to efficient energy utilization of system needs in the context of Bluetooth devices.

15:40 - 17:00

The design, simulation, implementation, and testing techniques required for networked system-chips are complex, as are the metrics to evaluate the performance. The diversity of macromodules required in such wireless systems on a chip represents a special challenge in almost all aspects of IC/System design. In this talk we present the state of the art in conceptualization and modeling of such systems, focusing on both the CAD problems that arise from such chips as well as on the methodology and tool flows.

Recommended Audiences :

Researchers, students and practicing engineers who are interested exploring design issues specific to on-chip implementations of networked embedded systems. CAD developers and researchers will develop an appreciation of the design tool requirements for wireless networked computing systems. Minimal familiarity with VLSI design, communications basics and computer programming is assumed.