Physical Chip Implementation - Hot Spots and Best Practices

A reliable physical implementation path from RTL to GDSII is more than the sum of its parts. Successful chip implementation must focus on time, resource constraints must be met. For example, a COT team with limited CAD resources must usually rely on a mostly off-the-shelf flow, unlike the team at an ASIC design center or IDM. This tutorial including specifics of vendor tools, tool-independent technology considerations, and insight into internal design capabilities. After establishing a baseline overall physical implementation methodology,

1. Early decisions in project bringup, including use of cores and other third-party IP, use of hierarchy, RTL practices (e.g., registered-in / of test strategy (e.g., scan BIST), pad layout implications, and choice of library.

2. Modern timing optimization and closure methodology at synthesis, placement, and detailed routing stages of implementation, using degrees of freedom such as fanout tree rebuilding, repeater/buffer insertion, sizing, and rewiring. The discussion will center on use of recent integrated placement and timing convergence tools, and also include congestion management in synthesis and RTL coding, as well as calibration and proper use of timing-driven features.

3. Signal integrity methodology, including management of crosstalk-induced noise and delay variation, inductance modeling, IR drop and ground bounce.

4. Hierarchy management, including advantages and disadvantages of hierarchical vs. flat, with respect to repeater insertion, pin assignment, hierarchy reconciliation, and performance macromodeling and analysis.

5. Floorplanning, including (i) creation of P&R blocks from the logical hierarchy, (ii) the use of abutment, repeater blocks, and bonus/spare cells and interconnects within the range of floorplanning approaches, (iii) consequences of area-I/O vs. peripheral I/O, and and datapath planning.

6. Methodology for on-chip power and clock planning and distribution.

7. Verification issues, including manufacturability (antenna rule design and verification, area fill sub-flow, etc.), overall physical design integration issues (DRC/LVS), and the range of necessary equivalence checks.

8. Packaging, including flip-chip and I/O cell issues, system/ package/chip codesign issues, and VDD/VSS and I/O distribution.

9. Other issues as time permits, including (i) adoption of new and innovative design tools and technologies, and (ii) the role of design verification, validation and integration (third-party IP issues, test benches, use of automated test and lab equipment, etc.).

Energy-Aware Networked Multimedia Systems: Modeling, Analysis and Optimization

Nowadays, people see more and more the need for portable embedded multimedia appliances capable of handling advanced algorithms required for all forms of communication (text, audio, video). In current System-On-Chip (SOC) design, power constraints can easily limit the number of media functions that can be integrated on the same chip. The power concern is particularly important for mobile multimedia applications where the battery lifetime severely limits the range of design options that one can consider for meeting all the other media quality requirements.

Power concerns are even more important in the context of newly software resources, that can be shared across multiple multimedia applications. Such design platforms consist of both fixed processing resources (e.g. Application Specific Integrated Circuits or ASICs) and programmable resources (e.g. general purpose and DSP processors, memories) that co-operate to run the target application (e.g. MPEG-2 audio/ video, e-mail, web, security, etc.). The overall goal of successful SOC design is then to find the best mapping of the target application onto these architectural resources, while satisfying a set imposed design constraints (e.g. minimum power dissipation, minimum area, maximum performance, etc.) and specified QoS metrics (e.g. end-to-end latency, jitter, loss rate) which directly impact the media quality.

In this tutorial, we plan to address the fundamental issues in the design and optimization of modern mobile multimedia systems (from both hardware and software perspectives) and illustrate the potential power/performance trade-offs and their impact on media quality. Most notably, the transition from desktop multimedia to portable multimedia based on heterogeneous design platforms brings concurrency and communication as key players in system-level modeling, analysis and optimization of these systems. For complex multimedia systems composed of many heterogeneous components that interact and communicate, early power/performance estimation and QoS-based power management are the critical steps for judicious allocation of the on-chip resources. This is particularly important since the on-chip resources are very limited compared to the available resources in desktop multimedia systems.

As a practical means, we will use examples from the design of the Apollo Testbed to illustrate concepts and methods for dynamic voltage and frequency scaling, power management and power-efficient encoding techniques. MPEG-2 will be featured as the driver application to illustrate the impact of different design choices on multimedia systems where the QoS requirements vary considerably and power and buffering resources are very limited. For such systems, the ability to explore many application-architecture mappings using different computational resources and communication schemes, while trying to satisfy tight QoS requirements, becomes of crucial importance.

Target Audience:

This tutorial is intended for researchers, engineers, educators, students interested in gaining a deep understanding of the next generation of portable information devices which, besides text and audio, will have to support complex continuous multimedia applications. The presentation is intended for people with or without multimedia background, with basic knowledge of VLSI and design automation issues. Ultimately, the main objective is to bring together multimedia systems designers and CAD tools developers and offer them a common perspective and the intuition behind critical issues which shape the evolution of the next generation of mobile multimedia.

C-based System Design Languages: SystemC and SpecC

There are varieties of C-based or C-related languages for such purposes, but the most influencing ones are currently SystemC and SpecC. These languages are similar in that both are based on C language and use essentially the same ways to describe system level behaviors, but they are different in the use of C/C++ languages. SystemC is within C++ language in terms of syntax, but SpecC is an extension to C language.

This tutorial gives introduction to both SystemC and SpecC from the aspects of languages themselves and their intended design methodologies. Instead of just giving language definition and basic issues, the intended design methodologies that are assumed in SystemC and SpecC are also clearly explained, which gives very good overviews and merits/ demerits on the languages to designers when they plan to use either SystemC or SpecC.

The tutorial has two parts which describe most recent status SystemC and SpecC. The SystemC part will be given in the two morning sessions and the SpecC part will be given in the two afternoon sessions.

SystemC part (given in the two morning sessions):

This part of the tutorial will provide an introduction to SystemC and its actual use in design flows for today¡Çs complex systems on chips. We will first present the motivation for the SystemC language and provide a review of the technical architecture and capabilities of SystemC 2.0. We will then present a practical example of SystemC v2.0 use, transaction level modeling (TLM) of a system for validation and architectural refinement.

Next we will look at some upcoming enhancements to SystemC. We will describe how SystemC 3.0 will enable abstract software and RTOS modeling. We will show how the upcoming SystemC verification library can be used to create intelligent testbenches using transaction-based verification, by providing features such as constrained randomization and transaction recording to enable effective design debugging and analysis.

SpecC part (given in the two afternoon sessions):

SpecC language version 2.0 is now available! One of the key features of SpecC 2.0 is the support of hardware design at the register transfer level (RTL). This session will give an introductory presentation of the SpecC language specification and the SpecC design methodology for embedded systems.

Next two excellent methodologies and tool-chains for the development of embedded systems with SpecC will be shown. Both case studies cover many areas of system design including system modeling, validation, HW/SW partitioning, interface synthesis, highlevel synthesis, and co-simulation. RT level hardware design is also covered by use of the new RTL features of SpecC 2.0.

Target Audience:

System, software and hardware designers of embedded systems who have some basic knowledge on hardware design methodologies and hardware design flows.

What can be obtained from the tutorial:

Basic knowledge on C-based design languages, SystemC and SpecC, Design methodologies that are supported by SystemC and SpecC, What can be done and what are difficult to be done with SystemC and SpecC, How SystemC or SpecC can smoothly be introduced to the design environment, How to describe HW/SW behaviors in Cbased languages.

Power, Timing, and Signal Integrity in SoC Designs

In this tutorial, we will first discuss detailed interconnect modeling for noise and timing. In the submicron and subnanometer domains, the effects of electric and magnetic fields interact in non-obvious ways. An overview of electromagnetic effects and their modeling will be discussed. Partial element equivalent circuit (PEEC) method will be outlined as an elegant and efficient way to interface pure electromagnetics to circuits that are more familiar to designers. Simplifying quasi-static assumptions will be given which will allow for much simpler models. The above models have to be fed into timing, noise and clock analysis to be useful. Model reduction techniques will be described as a method to reduce the parasitics database bottleneck. The impact of capacitive noise, resistive loss on attackers, driver size, and inductive noise will be detailed. A comparison between capacitive and inductive noise and their neighborhoods of influence will be detailed. Noise-on-timing effects will also be analyzed and explained. Inductive modeling will be of prime interest in clock analysis and will be described, both for clock grids and clock trees.

We then present efficient extraction approaches that can be used during iterative physical design and verification. We discuss characteristics of capacitance and inductance. These characteristics lead to the 2.5D capacitance extraction and table or formula based inductance extraction, and also help to understand interconnect design freedoms to minimize noise. We also present complexity-efficient RLC circuit model generation.

Further, we discuss power and current estimation with dynamic power management. Power gains an increasing importance in SoC designs, and dynamic power management (DPM) has been proposed to reduce power dissipation, Considering DPM, we present first power estimation and thermal calculation at system micro-architecture level and then estimation of current and power at RT level.

Finally, we present modeling and analysis of power supply network. According to the international technology roadmap for semiconductors, the power supply voltage will drop below 1 volt in the next decade. With the noise margin less than a few hundred millivolts, the control of power supply noise will be critical in determining the performance and reliability of integrated circuits. We will present the general methodology and modeling techniques for a complete and accurate full-chip power supply noise analysis. We will discuss how to estimate the switching current at each level of design. We will also address the transient noise associated with clock gating, as it becomes one of the most effective means to improve power efficiency. A comprehensive analysis of a 1.6 GHz microprocessor chip will be shown to illustrate the various design optimization techniques, such as decoupling capacitor placement, to mitigate the potential noise problem.

High-Speed CMOS Circuit Design

This tutorial surveys techniques for high-speed CMOS circuit design with emphasis on combinational and sequential logic design. It begins with back-of-the-envelope techniques for estimating and minimizing delay using the method of logical effort. It reviews the tradeoffs among the important circuit families including static CMOS, pseudo-nMOS, pass transistors, and domino logic. The timing constraints for sequencing elements including flip-flops, transparent latches, and pulsed latches are examined and skew-tolerant static and dynamic techniques are explored. Clock skew limits the performance of high-speed systems and is becoming more expensive to control as a fraction of the clock cycle. Clock distribution networks are analyzed for the skew they introduce. The skew between nearby elements can be much less than that across the chip so timing analyzers must be able to handle different amounts of skew on different paths.