Topic Subcommittees/ASP-DAC 2005
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(**/* indicate the subcommittee chair/vice-chair) | |||||||||||||||||||||||||||||||||||||||||
Topic [1]:
System Level Design Methodology System VLSI and SOC design methods, System specification, Specification languages, Design languages, Design reuse and IPs , Core-based design, Rapid prototyping, Low power system design, etc. |
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** Deng-Yuan (David) Chen IDT-NEWAVE Technology Co., Ltd. Shanghai 200233, P. R. China E-mail: david.chen@nw.idt.com * Soonhoi Ha Seoul National University, Korea E-mail: sha@snu.ac.kr; sha@hana.or.kr * S. K. Nandy Supercomputer Education and Research Center Indian Institute of Science, Bangalore 560 012, India E-mail: nandy@serc.iisc.ernet.in |
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1 Prof. Shinji Kimura Waseda University E-mail: shinji_kimura@waseda.jp 2 Dr. Sunil D. Sherlekar Head, Centre for Excellence for Embedded Systems, Tata Consultancy Services E-mail: sds@blore.tcs.co.in http://www.tcs.com 3 Dr. Balakrishnan S. Senior Scientist, Embedded Systems Architectures on Silicon Philips Research Laboratories Eindhoven, The Netherlands Phone: +31 40 27 43272 Fax: +31 40 27 44639 E-mail: srinivasan.balakrishnan@philips.com 4 Prof. Ed Deprettere Leiden Embedded Research Center, Leiden University, The Netherlandsm E-mail: edd@liacs.nl 5 Prof. Jun Dong Cho Department of Electronic and Computer Engineering SungKyunKwan Univ. Korea Phone: +82-331-290-7127 Fax: +82-2-290-7192 E-mail: jdcho@skku.ac.kr 6 Prof. Soo-Ik Chae Head of Center for SoC Design Technology, Seoul National University Phone: +82-2-880-5457 Fax: +82-2-888-1691 E-mail: chae@sdgroup.snu.ac.kr 7 Dr. Ando Ki Dynalith Systems Phone: +82-42-862-6411 E-mail: adki@garden.dynalith.com 8 Prof. Matthew Jacob Supercomputer Education and Research Center, Indian Institute of Science, India E-mail: mjt@serc.iisc.ernet.in 9 Ms. Manvi Agarwal CAD Lab., Indian Institute of Science, India E-mail: manvi@cadl.iisc.ernet.in 10 Mr. G. Surendra CAD Lab., Indian Institute of Science, India E-mail: surendra@cadl.iisc.ernet.in; surendra@rishi.serc.iisc.ernet.in 11 Mr. Subhasis Banerjee CAD Lab., Indian Institute of Science, India E-mail: subhasis@cadl.iisc.ernet.in; surendra@rishi.serc.iisc.ernet.in 12 Miroslav Velev Reservoir Labs, USA E-mail: mvelev@ece.gatech.edu |
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Topic [2]: Embedded
and Real-Time Systems Hardware-software co-design, Co-simulation, Co-verification, Real-time OS and middleware, Design language for embedded systems, Compilation Techniques, etc. |
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** Jihua Chen National University of Defence Technology Changsha 410073, P. R. China E-mail: jhchen@nudt.edu.cn * X. Sharon Hu University of Notre Dame, Notre Dame, IN 46556, USA E-mail: shu@cse.nd.edu * Chong-Min Kyung KAIST, Korea E-mail: kyung@ee.kaist.ac.kr |
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1 Zebo Peng Linkoping University, Sweden 2 Insup Lee University of Pennsylvania, USA 3 Luciano Lavagno Politecnico di Torino, Italy Cadence Labs, USA 4 Chenglian Peng Fudan University, P. R. China E-mail: clpeng@fudan.edu.cn 5 Shu Han Peking University, Beijing 100084, P. R. China E-mail: hanshu@mprc.pku.edu.cn 6 Mingyan Yu Haerbin University of Technology, P. R. China 7 Haibin Sheng Zhejing University, P. R. China E-mail: shehb@vlsi.zju.edu.cn 8 JoAnn Paul Carnegie Mellon University, USA E-mail: jpaul@ece.cmu.edu 9 Gang Quan University of South Carolina, USA E-mail: gquan@cse.sc.edu 10 Donatella Sciuto Politecnico di Milano, Italy E-mail: sciuto@elet.polimi.it 11 Prof. In-Cheol Park Department of EECS, KAIST E-mail:icpark@ee.kaist.ac.kr 12 Prof. Youngsoo Shin Department of EECS, KAIST E-mail:youngsoo@ee.kaist.ac.kr |
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Topic [3]:
Behavioral / Logic Synthesis and Optimization Behavioral / RT synthesis, Optimization techniques in logic design, Library mapping, Interaction between logic design and layout, IP-core design, Sequential and asynchronous logic synthesis, Hardware algorithms, etc. |
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** Jinian Bian Tsinghua University, Beijing 100084, P. R. China E-mail: bianjn@tsinghua.edu.cn * Jianwen Zhu University of Toronto, Canada E-mail: jzhu@eecg.toronto.edu |
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1 Reinaldo A Bergamaschi IBM T. J. Watson Research Center E-mail: berga@us.ibm.com 2 Shih-Chieh Chang Tsing Hua University, Hsin-Chu E-mail: scchang@cs.nthu.edu.tw 3 Rolf Drechsler University of Bremen E-mail: drechsle@informatik.uni-bremen.de 4 Jungang Han Xian Institute of Posts&Telecoms E-mail: hjg@xiyou.edu.cn; hanjungang@yahoo.com 5 Yunjian Jiang Magma Design Automation 6 Taewhan Kim Seoul National University E-mail: tkim@ssl.snu.ac.kr 7 Sikun Li The National University of Defense Technology E-mail: skli@nudt.edu.cn 8 Tsutomu Sasao Kyushu Institute of Technology E-mail: sasao@cse.kyutech.ac.jp 9 Feng Shi Beijing Institute of Technology E-mail: sfsbt@263.net 10 Mingcheng Zhu Shenzhen University E-mail: zhumc@szu.edu.cn, mgmgmg@21cn.com |
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Topic [4]:
Validation and Verification for Behavioral / Logic Design Logic simulation, Simulation engine, Symbolic simulation, Formal verification, Binary decision diagram, Equivalence checking, Transaction-level / RTL and gate level modng and validation, etc. |
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** Jin Yang Intel Corporation, Hillsboro, OR 97124-5961, USA E-mail: jin.yang@intel.com * Yunshan Zhu Synopsys, Inc., CA 94043, USA E-mail: Yunshan.Zhu@synopsys.com * Alan J. Hu University of British Columbia, Vancouver, BC V6T 1Z4, Canada E-mail: ajh@cs.ubc.ca |
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1 KC Chen Cadence, USA E-mail: kcchen@cadence.com 2 Kwang-Ting (Tim) Cheng University of California at Santa Barbara, USA E-mail: timcheng@ece.ucsb.edu 3 Ed Clarke Carnegie Mellon University, USA E-mail: emc@cs.cmu.edu 4 Masahiro Fujita University of Tokyo, Japan E-mail: fujita@ee.t.u-tokyo.ac.jp 5 Norris Ip Jasper, USA E-mail: ip@jasper-da.com 6 Mahesh Iyer Synopsys, USA E-mail: Mahesh.Iyer@Synopsys.COM 7 Robert B Jones Intel, USA E-mail: robert.b.jones@intel.com 8 Yuan Lu Broadcom, USA E-mail: ylu@broadcom.com 9 Yinghua Min Institute of Computing Technology, CAS, P. R. China E-mail: min@ict.ac.cn 10 Carl Pixley Synopsys, USA E-mail: Carl.Pixley@Synopsys.COM 11 Weimin Wu Tsinghua University, P. R. China E-mail: wuwm@mail.tsinghua.edu.cn 12 Tomohiro Yoneda National Institute of Informatics, Japan E-mail:yoneda@nii.ac.jp |
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Topic [5]:
Circuit Optimization and Simulation Circuit modng, Circuit simulation, Circuit extraction, Cell library characterization and generation, Circuit characterization, Clock / power / ground distribution, Signal integrity issues, etc. |
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** Huazhong Yang Tsinghua University, Beijing 100084, P. R. China E-mail: yanghz@tsinghua.edu.cn * Sheldon X.-D. Tan University of California at Riverside, CA 92521-0204, USA E-mail: stan@ee.ucr.edu |
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1 Dr. Anirudh Devgan |
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