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ASP-DAC 2006 Archives
2D-1
| Title | Electrothermal Analysis and Optimization Techniques for Nanoscale Integrated Circuits |
| Author | *Yong Zhan, Brent Goplen, Sachin S. Sapatnekar (University of Minnesota, United States) |
| Abstract | With technology scaling, on-chip power densities are growing steadily, leading to the point where temperature has become an important consideration in the design of electrical circuits. This paper overviews several methods for the analysis and optimization of thermal effects in integrated circuits. Thermal analysis may be carried out efficiently through the use of finite difference methods, finite element methods, or Green function based methods, each of which provides different accuracy-computation tradeoffs, and the paper begins by surveying these. Next, we overview a restricted set of thermal optimization methods, specifically, placement techniques for thermal heat-spreading, and then we conclude by summarizing a set of future directions in electrothermal design. |
| Slides (pdf file) | 2D-1 |
2D-2
| Title | Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems |
| Author | *Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava (University of California, Santa Barbara, United States) |
| Abstract | Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This paper will provide a broad overview of various ET effects in nanoscale VLSI and highlight both technology and design choices that are thermally-aware. The paper ends with a brief discussion of electrothermal issues in emerging 3-D ICs and highlights the advantages of employing hybrid Carbon Nanotube-Cu interconnects in both 2-D and 3-D designs. |
| Slides (pdf file) | 2D-2 |
2D-3
| Title | Area Optimization for Leakage Reduction and Thermal Stability in Nanometer Scale Technologies |
| Author | *Ja Chun Ku, Yehea Ismail (Northwestern University, United States) |
| Abstract | Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however that the use of minimum area does not result in the minimum power and/or delay in nanometer scale technologies due to thermal effects, and in some cases, may result in thermal runaway. A methodology using area as a design parameter to reduce the leakage power, and prevent thermal runaway is presented. A 16-bit adder example in a 70nm technology shows a total power savings of 17% with 15% increase in area, and no increase in delay. The power savings using this technique are expected to increase in future technologies. |
| Slides (pdf file) | 2D-3 |
2D-4
| Title | Compact Thermal Models for Estimation of Temperature-dependent Power/Performance in FinFET Technology |
| Author | Aditya Bansal, Mesut Meterelliyoz (Purdue University, United States), Siddharth Singh (Osmania Univerisity, India), Jung Hwan Choi, Jayathi Murthy, *Kaushik Roy (Purdue University, United States) |
| Abstract | With technology scaling, elevated temperatures caused by increased power density create a critical bottleneck modulating the circuit operation. With the advent of FinFET technologies, cooling of a circuit is becoming a bigger challenge because of the thick buried oxide inhibiting the heat flow to the heat sink and confined ultra-thin channel increasing the thermal resistivity. In this work, we propose compact thermal models to predict the temperature rise in FinFET structures. We develop cell-level compact thermal models for standard INV, NAND and NOR gates accounting for the heat transfer across the six faces of a cell. Temperature maps of benchmark circuits exhibit close correspondence with dynamic power maps because of confined regions of heat generation separated by low thermal conductivity material. It is illustrated that temperature-aware timing analysis is imperative, because of high inter-cell temperature gradient. Accurate prediction of temperature in the early phase of design cycle will give valuable estimation of power/performance/reliability of a circuit block and will guide in the design of more robust circuits. |
| Slides (pdf file) | 2D-4 |