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ASP-DAC 2006 Archives
4B-1
| Title | High-Level Architecture Exploration for MPEG4 Encoder with Custom Parameters |
| Author | *Marius Bonaciu, Aimen Bouchhima, Wassim Youssef, Xi Chen (TIMA Laboratory, France), Wander Cesario (MND, France), Ahmed Jerraya (TIMA Laboratory, France) |
| Abstract | This paper proposes the use of a high-level architecture exploration method for different MPEG4 video encoders using different customization parameters. The targeted architecture is a heterogeneous MP-SoC which may include up 2 coarse grain SIMD (task level SIMD) subsystems to perform the computations. The customization parameters are related to video resolution, frame rate, Communication Network, level of parallelism and CPU types. These parameters are determined during the high-level architecture exploration, by estimating the archi-tecture performances at early stages of the design flow. Experiments shows that the error factor of these high-level performances estimations are less than 10% compared to those obtained with final manually implemented RTL architecture. This method was used successfully for exploration of different MPEG4 architecture configurations with differ-ent customization parameters. We consider these experiments a break-through because they show how a complex design can be mastered through a set of pragmatic choices. |
| Slides (pdf file) | 4B-1 |
4B-2
| Title | Programmable Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method |
| Author | *Shinobu Nagayama (Hiroshima City University, Japan), Tsutomu Sasao (Kyushu Institute of Technology, Japan), Jon Butler (Naval Postgraduate School, United States) |
| Abstract | This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) for trigonometric, logarithmic, square root, and reciprocal functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each segment. Thus, we can implement fast and compact NFGs for a wide range of functions. Implementation results on an FPGA show that: 1) our NFGs require only 4% of the memory needed by NFGs based on the linear approximation with non-uniform segmentation; and 2) our NFGs require only 22% of the memory needed by NFGs based on the 5th-order approximation with uniform segmentation. Our automatic synthesis system generates such compact NFGs quickly. |
| Slides (pdf file) | 4B-2 |
4B-3
| Title | An Automated Design Flow for 3D Microarchitecture Evaluation |
| Author | *Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang (University of California, Los Angeles, United States) |
| Abstract | Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area and power dissipation in nanometer technologies, its impact on system performance is still poorly understood due to the lack of tool and systematic flow to evaluate 3D microarchitectures integration. The contribution of this paper is the development of an automated physical design flow for 3D architectures evaluation, named MEVA-3D, which includes 3D floorplanning, routing and automated thermal via insertion, and associated die size, performance, and thermal modeling capabilities. We apply this flow to some simple out-of-order superscaler microprocessor design to evaluate the performance and thermal behavior in 2D and 3D designs, and demonstrate the value of MEVA-3D in providing quantitative evaluation results to guide 3D architecture designs. In particular, we show that it is feasible to manage the thermal challenge with the use of a combination of thermal vias and double-sided heat sinks, and report modest system performance gain in 3D design for these simple test examples. |
| Slides (pdf file) | 4B-3 |
4B-4
| Title | Optimal Topology Exploration for Application-Specific 3D Architectures |
| Author | Ozcan Ozturk, Feng Wang, *Mahmut Kandemir, Yuan Xie (Pennsylvania State University, United States) |
| Abstract | As technology scales, increasing interconnect costs make it necessary to consider alternate ways of building integrated circuits. One promising option along this direction is 3D architectures where a stack of multiple device layers, with direct vertical tunneling through them, are put together on the same chip. In this paper, we explore how processor cores and storage blocks can be placed in a 3D architecture to minimize data access costs under temperature constraints. This process is referred to as the topology exploration. Using integer linear programming, we compare the best 2D placement with the best 3D placement, and show through experiments with both single-core and multi-core systems that the 3D placement generates much better results (in terms of data access costs) under the same temperature bounds. We also discuss the tradeoffs between temperature constraint and data access costs. |
| Slides (pdf file) | 4B-4 |
4B-5
| Title | Task Placement Heuristic Based on 3D-Adjacency and Look-Ahead in Reconfigurable Systems |
| Author | Jesus Tabero (Instituto Nacional de Tecnica Aeroespacial, Spain), Julio Septien, Hortensia Mecha, *Daniel Mozos (Universidad Complutense de Madrid, Spain) |
| Abstract | To get efficient HW management in 2D Reconfigurable Systems, heuristics are needed to select the best place to locate each arriving task. We propose a technique that locates the task next to the borders of the free area for as many cycles as possible, trying to minimize the area fragmentation. Moreover, we combine it with a look-ahead heuristic that allows delaying the scheduling of a task to the next event, increasing the solution search space. |
| Slides (pdf file) | No slides |