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ASP-DAC 2006 Archives
7B-1
| Title | Equivalent Circuit Modeling of Guard Ring Structures for Evaluation of Substrate Crosstalk Isolation |
| Author | *Daisuke Kosaka, Makoto Nagata (Kobe University, Japan) |
| Abstract | Abstract A substrate-coupling equivalent circuit can be derived for an arbitrary guard ring test structure by way of F-matrix computation. The derived netlist represents a unified impedance network among multiple sites on a chip surface and allows circuit simulation for evaluation of isolation effects provided by guard rings. Geometry dependency of guard ring effects attributes to layout patterns of a test structure, including such as area of a guard ring as well as location distance from the circuit to be isolated by the guard ring. In addition, structural dependency arises from vertical impurity concentrations such as p+, n+, and deep n-well, which are generally available in a deep-submicron CMOS technology. The proposed simulation based prototyping technique of guard ring structures can include all these dependences and thus can be strongly helpful to establish isolation strategy against substrate coupling in a given technology, in an early stage of SoC developments. |
| Slides (pdf file) | 7B-1 |
7B-2
| Title | A New Boundary Element Method for Accurate Modeling of Lossy Substrates with Arbitrary Doping Profiles |
| Author | *Xiren Wang, Wenjian Yu, Zeyi Wang (EDA Lab., Dept. of Computer Science & Technology, Tsinghua University, China) |
| Abstract | It is important to model substrate couplings for SoC/mixed-signal circuit designs. After introducing the continuation equation of full current in lossy substrates, we present a new direct boundary element method (DBEM), which can handle the substrates with arbitrary doping profiles. Three techniques can speed up the DBEM remarkably, which include reusing coefficient matrices for multiple-¬frequency calculation, condensing the linear system, and sparsifying coefficient matrix. Numerical experiments illustrate that DBEM has high accuracy and high efficiency, and is versatile for arbitrary doping profiles. |
| Slides (pdf file) | 7B-2 |
7B-3
| Title | Parasitics Extraction Involving 3-D Conductors based on Multi-layered Green's Function |
| Author | Zuochang Ye, *Zhiping Yu (Institute of Microelectronics, Tsinghua University, China) |
| Abstract | An efficient algorithm for three-dimensional (3-D) capacitance extraction on multi-layered and lossy substrate is presented. The new algorithm represents a major improvement over the quasi-3D approach used in Green's function based solvers and takes into consideration of the side-wall effects of the contacts. |
| Slides (pdf file) | 7B-3 |
7B-4
| Title | Signal-Path Driven Partition and Placement for Analog Circuit |
| Author | *Di Long, Xianlong Hong, Sheqin Dong (Tsinghua University, China) |
| Abstract | This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three observations: thinking of hierarchical design for analog, structural feature of circuit based on signal-path, requirements of matching/symmetry constraint and the reduction of parasitics. The thinking of hierarchical design makes the whole analog circuit divided into core-circuit and bias-circuit. So, the algorithm is designed as two independent steps: core-circuit is placed firstly, and then bias-circuit. The structural feature of circuit based on signal-path and the requirement of matching/symmetry constraint decide the placement pattern of core-circuit. The reduction of parasitics requires the algorithm to select the optimal variants to realize the placement. Experimental results demonstrate that this algorithm can generate the compact layout with high performance and it is universal and effective. |
| Slides (pdf file) | 7B-4 |
7B-5
| Title | An Approach to Topology Synthesis of Analog Circuits Using Hierarchical Blocks and Symbolic Analysis |
| Author | *Xiaoying Wang, Lars Hedrich (Department of Computer Science, University of Frankfurt, Germany) |
| Abstract | This paper presents a method of design automation for analog circuits, focusing on topology generation and quick performance evaluation. First we describe mechanisms to generate circuit topologies with hierarchical blocks. Those blocks are specialized by adding terminal information. The connection between blocks is in compliance with a set of synthesis rules, which are extracted from typical schematics in the literature. Symbolic analysis has been used to select an appropriate topology quickly. |
| Slides (pdf file) | 7B-5 |