ASP-DAC 2006 Archives


7C-1
Title Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications)
Author *Kenta Yamada, Noriaki Oda (NEC Electronics Corporation, Japan)
Abstract Timing closure in LSI design becomes more and more difficult. But the conventional interconnect RC extraction method have over-margins caused by its corner conditions settings. In this paper, statistical corner conditions using the independence of variations between process parameters and between interconnect layers are proposed. As a result, the fast-to-slow guardband decreases by half in average, compared to the conventional method. The proposed method is ready for implementation to LPE tools.
Slides (pdf file) 7C-1


7C-2
Title Speed Binning Aware Design Methodology to Improve Profit under Parameter Variations
Author Animesh Datta (Purdue University, United States), Swarup Bhunia (Case Western Reserve University, United States), Jung Hwan Choi, Saibal Mukhopadhyay, *Kaushik Roy (Purdue University, United States)
Abstract Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-aware yield model, based on which we present a statistical design methodology to improve profit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve the profitability of design over an initial yield-optimized design. We also propose an algorithm to determine optimal bin boundaries for maximizing profit with frequency binning. Finally, we present an integrated design methodology for simultaneous sizing and bin placement to enhance profit under an area constraint. Experiments on a set of ISCAS85 benchmarks show up to 26% (36%) improvement in profit for fixed bin (for simultaneous sizing and bin placement) with three frequency bins considering both leakage and delay bounds compared to a design optimized for 90% yield at iso-area.
Slides (pdf file) 7C-2


7C-3
Title Yield-Area Optimizations of Digital Circuits Using Non-dominated Sorting Genetic Algorithm (YOGA)
Author Vineet Agarwal, *Janet Wang (University of Arizona, United States)
Abstract With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged as one of the eĀ±cient way to subside the yield deterioration due to manufacturing variations. In the past single-objective optimization techniques have been used to optimize the timing variation whereas on the other hand multi-objective optimization techniques can provide a more promising approach to design the circuit. We propose a new algorithm called YOGA, based on multi-objective optimization technique called Non-dominated Sorting Genetic Algorithm (NSGA). YOGA optimizes a circuit in multi domains and provides the user with Pareto-optimal set of solutions which are distributed all over the optimal design spectrum, giving users the flexibility to choose the best fitting solution for their requirements. YOGA overcomes the disadvantages of traditional optimization techniques, while even providing solutions in very stringent bounds.
Slides (pdf file) 7C-3


7C-4
Title A Probabilistic Analysis of Pipelined Global Interconnect Under Process Variations
Author *Navneeth Kankani, Vineet Agarwal, Janet M Wang (University of Arizona, United States)
Abstract The main thesis of this paper is to perform a reliability based analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a novel delay metric named CPUA for estimation of interconnect delay probability density function considering process variations. Without considerable loss in accuracy, CPUA can achieve high computational efficiency even in a large space of random variables. We then propose a comprehensive probabilistic methodology for sampling transfers, on a shared latch inserted global interconnect, that highly improves the reliability of the interconnect. Improvements up to 125% are observed in the reliability when compared to deterministic sampling approach. It is also shown that dual phase clocking scheme for pipelined global interconnect is able to meet more stringent timing constraints due to its lower latency.
Slides (pdf file) 7C-4


7C-5
Title Yield-Preferred Via Insertion Based on Novel Geotopological Technology
Author Fangyi Luo (University of California, Santa Cruz, United States), *Yongbo Jia (Nannor Technologies, Inc., United States), Wayne Wei-Ming Dai (University of California, Santa Cruz, United States)
Abstract Yield-preferred via insertion is an effective method to reduce the yield loss caused by via failures. The existing methods to apply the redundant-cut vias in metal layers are not efficient nor adequate. In this paper, we present an effective and efficient yield-preferred via insertion method based on a novel geotopological layout platform, GEOTOP. Our method chooses the most yield-favored via candidate and insert it into the layout without causing any design rule violations. Experiments with real industry designs show that our method can achieve very high rate of yield-preferred via without increasing the design die size within acceptable running time.
Slides (pdf file) 7C-5