ASP-DAC 2006 Archives


8C-1
Title Efficient Early Stage Resonance Estimation Techniques for C4 Package
Author *Jin Shi, Yici Cai (Department of Computer Science and Technology, Tsinghua University, China), Shelton X-D Tan (Department of Electrical Engineering, University of California at Riverside, United States), Xianlong Hong (Department of Computer Science and Technology, Tsinghua University, China)
Abstract In this paper, we study the relationship of the C4 package resonance effects and logical switching timing correlations, which was less investigated in the past. We show that improper logic designs with some special timing correlations can lead to adverse large voltage drops due to resonance effects in the widely used C4 package. We first present the numerical analysis results on industry C4 package circuits to demonstrate resonance phenomenon. Then we propose a simple algorithm to compute the worst case logical timing correlations among cells leading to resonance. Finally, we develop an efficient technique in early logic design stage to estimate the resonance risk. Experiment results demonstrate the effectiveness of the proposed method for the accurate prediction of the resonance effect in C4 package.
Slides (pdf file) 8C-1


8C-2
Title Parallel-Distributed Time-Domain Circuit Simulation of Power Distribution Networks with Frequency-Dependent Parameters
Author *Takayuki Watanabe (University of Shizuoka, Japan), Yuichi Tanji (Kagawa University, Japan), Hidemasa Kubota, Hideki Asai (Shizuoka University, Japan)
Abstract In this paper, we focus on the verification of the PCB/Package power integrity, which becomes very important for the design of state-of-art high speed digital circuits. The simulation of power distribution networks (PDNs) of the PCB/Package, which can be modeled as a large number of RLC lumped components, is a time-consuming task for using the conventional circuit simulator, such as SPICE. For this purpose, we propose a parallel-distributed time-domain circuit simulation algorithm based on LIM. Furthermore, an effective modeling of frequency-dependencies of the PDNs, such as skin effects and dielectric losses, to solve by LIM is proposed.
Slides (pdf file) 8C-2


8C-3
Title Power Distribution Techniques for Dual VDD Circuits
Author *Sarvesh Hemchandra Kulkarni, Dennis Sylvester (University of Michigan, United States)
Abstract Extensive research has proposed the use of multiple on-die power supplies (VDD) for reducing power consumption in CMOS circuits. We present a detailed study and design techniques for power delivery systems in dual VDD CMOS circuits. We first show that the total current to be delivered by the voltage supplies is significantly reduced (by 27%−46%) in dual VDD circuits. This current reduction prompts various design strategies that can be employed to design the power delivery system. We describe issues that arise at the system, board and package levels and propose a high-level model for the same. We then provide a new placement driven approach for designing on-die dual VDD power grids. Compared to already existing methods, the dual VDD grids generated by our approach reduce the worst case and average voltage drop by up to 12.3% and 6.8% respectively with no area overhead and sometimes improving wire congestion. We also show that dual VDD circuits can afford lower on-die decoupling capacitance budgets.
Slides (pdf file) 8C-3


8C-4
Title Calculating Frequency-Dependent Inductance of VLSI Interconnect by Complete Multiple Reciprocity Boundary Element Method
Author *Changhao Yan, Wenjian Yu, Zeyi Wang (Department of Computer Science and Technology, Tsinghua University, China)
Abstract A complete multiple reciprocity method (CMRM), usually for the eigenvalue analysis of Helmholtz equation, is introduced to the BEM for frequency-dependent inductance extraction. Several approaches are proposed to resolve the problem of "ill-conditioned" series encountered when applying the CMRM practically. Using the BEM combined with CMRM, the major operations of calculating the numerical integrals for a frequency point become reusable, so that inductance extraction for a frequency range is greatly accelerated. Numerical results verify the accuracy and efficiency of the proposed method.
Slides (pdf file) 8C-4


8C-5
Title Controlling Inductive Cross-talk and Power in Off-chip Buses using CODECs
Author Brock LaMeres (Agilent Technologies Inc., United States), Kanupriya Gulati, *Sunil Khatri (Dept of Electrical Engg., Texas A&M University, United States)
Abstract The parasitic inductances within IC packaging cause supply bounce as well as glitches on the signal pins, significantly limiting the frequency of high-speed inter-chip communication.. Also, off-chip communication contributes a large fraction of the total system power. Until recently, the parasitic inductance problem was addressed by aggressive package design, which is expensive. In this work we present a technique to encode the off-chip data transmission to i) limit bounce on the supplies ii) reduce glitching caused by inductive signal coupling from neighboring signals iii) limit the edge degradation of signals due to mutually inducted voltages from neighboring switching signals and iv) control the total power consumption of the I/O logic. All these factors are modeled in a unified mathematical framework. Our experimental results show that the proposed encoding based techniques result in reduced supply bounce and signal glitching due to inductive cross-talk, closely matching the theoretical predictions. Also, we show that the bus size overhead is reasonable even after stringent power reduction constraints are imposed. We demonstrate that the overall bandwidth of a bus actually increases by 100% over an unencoded bus, using our technique with inductive constraints only (even after accounting for the encoding overhead). When the power constraints were added (to limit the power to 20% of worst case switching power) in addition to the inductive constraints, the bandwidth was again 100% improved over the unencoded bus. The asymptotic bus size overhead depends on how stringent the user-specified power and inductive cross-talk parameters are. We have validated our approach by simulating it in an ASIC setting as well as prototyping and testing it in an FPGA environment.
Slides (pdf file) 8C-5