Highlights

	Keynote Addresses
	Keynote I : Wednesday, January 25, 9:00-10:00, Small Auditorium, 5F Automotive Electronics: Steady Growth for Years to Come Alberto Sangiovanni-Vincentelli The Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Science, Univ. of California, Berkeley and Chief Technology Advisor, Member of the Board and Co-founder, Cadence Design Systems, United States
	Keynote II : Thursday, January 26, 9:00-10:00, Small Auditorium, 5F Challenging Device Innovation Satoru Ito President & CEO RENESAS Technology Corp., Japan
	Keynote III : Friday, January 27, 9:00-10:00, Small Auditorium, 5F Platform Structure for Digital Products Development (title changed) Yukichi Niwa Senior Advisory Director, Group Executive of Platform Technology Development Headquarters, CANON INC., Japan

	Special Sessions
	1D : Wednesday, January 25, 10:15-12:20, Room 416+417, 4F Presentation + Poster Discussion: University Design Contest
	2D : Wednesday, January 25, 13:30-15:35, Room 416+417, 4F Invited Talks: Electrothermal Design of Nanoscale Integrated Circuits
	3D : Wednesday, January 25, 16:00-18:05, Room 416+417, 4F Invited Talks: Flash Memory in Embedded Systems
	4D : Thursday, January 26, 10:15-12:20, Room 416+417, 4F Invited Talks: Open Access Overview
	7D : Friday, January 27, 10:15-12:20, Room 416+417, 4F Invited Talks + Panel Disucssion: H.264/AVC Design Challenges and Solutions

	Designers' Forum
	5D : Thursday, January 26, 13:30-15:30, Small Auditorium, 5F Invited Talks: Low Power Design
	6D: Thursday, January 26, 16:30-18:00, Small Auditorium, 5F Panel Discussion: Functional Verification -now and future-
	8D: Friday, January 27, 13:30-15:30, Small Auditorium, 5F Invited Talks: `Cell' Processor
	9D: Friday, January 27, 16:30-18:00, Small Auditorium, 5F Panel Disussion: Top 10 Design Issues by LSI Designers versus EDA Developers

	Tutorials
	Tutorial 1 (Full Day) : Tuesday, January 24, 9.30-17.00, Room 411+412, 4F DFM Tools and Methodologies for 65nm and Below
	Tutorial 2 (Full Day) : Tuesday, January 24, 9.30-17.00, Room 413, 4F High Performance Interconnect and Packaging
	Tutorial 3 (Half Day) : Tuesday, January 24, 9.30-12.30, Room 414+415, 4F Low Power / Low Leakage Technologies for Nanometer Era: System and Architecture Level Approaches
	Tutorial 4 (Half Day) : Tuesday, January 24, 14.00-17.00, Room 414+415, 4F Low Power / Low Leakage Technologies for Nanometer Era: Circuit and Device Level Approaches
	Tutorial 5 (Half Day) : Tuesday, January 24, 9.30-12.30, Room 416+417, 4F Basics and Practice of Current Functional Verification Methods
	Tutorial 6 (Half Day) : Tuesday, January 24, 14.00-17.00, Room 416+417, 4F SoC Communication Architectures: Current Practice, Research and Trends

Last Updated on: January 26, 2006