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The 11th Asia and South Pacific Design Automation Conference

Wednesday January 25, 2006

Session 1B Interconnect for High-End SoC (10:15 - 12:20)
Location: Room 413
Chair(s): Yoshinori Takeuchi (Osaka Univ., Japan), Juinn-Dar Huang (National Chiao-Tung Univ., Taiwan)

1B-1 (Time: 10:15 - 10:40)
TitleConstraint-Driven Bus Matrix Synthesis for MPSoC
Author*Sudeep Pasricha, Nikil Dutt (Univ. of California, Irvine, United States), Mohamed Ben-Romdhane (Conexant, United States)
Pagepp. 30 - 35
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1B-2 (Time: 10:40 - 11:05)
TitleImproving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection
Author*Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz (Univ. of Southampton, Great Britain)
Pagepp. 36 - 41
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1B-3 (Time: 11:05 - 11:30)
TitlePhysical Design Implementation of Segmented Buses to Reduce Communication Energy
Author*Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor (IMEC, Belgium)
Pagepp. 42 - 47
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1B-4 (Time: 11:30 - 11:55)
TitleCo-Synthesis of a Configurable SoC Platform based on a Network on Chip Architecture
Author*Mário Pereira Véstias, Horácio Neto (INESC-ID, Portugal)
Pagepp. 48 - 53
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1B-5 (Time: 11:55 - 12:20)
TitleCustomized SIMD Unit Synthesis for System on Programmable Chip - A Foundation for HW/SW Partitioning with Vectorization
AuthorMuhammad Omer Cheema, *Omar Hammami (ENSTA Paris, France)
Pagepp. 54 - 60
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