| Title | Constraint-Driven Bus Matrix Synthesis for MPSoC |
| Author | *Sudeep Pasricha, Nikil Dutt (University of California, Irvine, United States), Mohamed Ben-Romdhane (Conexant, United States) |
| Page | pp. 30 - 35 |
| Keyword | bus matrix, communication architecture synthesis, MPSoC |
| Abstract | Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based communication architectures consist of several parallel busses which provide a suitable backbone to support high bandwidth systems, but suffer from high cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9x component savings when compared to a full bus matrix and up to 3.2x savings when compared to a maximally connected reduced bus matrix. |
| Title | Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection |
| Author | *Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz (University of Southampton, Great Britain) |
| Page | pp. 36 - 41 |
| Keyword | network-on-chip, routing, input selection, switch, contention-aware |
| Abstract | The performance of Network-on-Chip (NoC) largely depends on the underlying routing techniques, which have two constituencies: output selection and input selection. Previous research on routing techniques for NoC has focused on the improvement of output selection. This paper investigates the impact of input selection, and presents a novel contention-aware input selection (CAIS) technique for NoC that improves the routing efficiency. When there are contentions of multiple input channels competing for the same output channel, CAIS decides which input channel obtains the access depending on the contention level of the upstream switches, which in turn removes possible network congestion. Simulation results with different synthetic and real-life traffic patterns show that, when combined with either deterministic or adaptive output selection, CAIS achieves significant better performance than the traditional first-come-first-served (FCFS) input selection, with low hardware overhead (<3%). |
| Title | Physical Design Implementation of Segmented Buses to Reduce Communication Energy |
| Author | *Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor (IMEC, Belgium) |
| Page | pp. 42 - 47 |
| Keyword | segmented bus, physical design, netlist topology, activity aware floorplanning |
| Abstract | The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of (long) wires. To limit this energy penalty,
segmented buses have gained interest in the architectural
community. However, the netlist topology and the physical design stage significantly influence the final communication energy cost. We present in this paper an automated way to implement a netlist consisting of hard macro blocks, which are interconnected with heavily
segmented buses in an energy optimal fashion for communication. We optimize the network wires energy dissipation in two separate, but related steps: minimizing the number of segments for active communication paths at the first step (block ordering), followed by the activity aware floorplanning step to minimize the physical length
of these segments. Energy gains of up to a factor of 4 are achieved compared to a standard system implementation using a shared bus. Especially, the block ordering step contributes significantly to the network energy optimization. |
| Title | Customized SIMD Unit Synthesis for System on Programmable Chip - A Foundation for HW/SW Partitioning with Vectorization |
| Author | Muhammad Omer Cheema, *Omar Hammami (ENSTA Paris, France) |
| Page | pp. 54 - 60 |
| Keyword | SIMD Synthesis, HW/SW Codesign, AltiVec Architecture, Vectorization |
| Abstract | Use of Single Instruction Multiple Data (SIMD) functional units enables multimedia systems to exploit parallelism to a higher degree resulting in significant system performance improvements. While implementation of whole SIMD system functionality for an application results in wastage of area resources, we have observed that for a specific multimedia application, we only need to implement a customized SIMD unit that is a subset of whole SIMD standard implementation. Based on this study, we have proposed an extension to the traditional system design and synthesis flow by integrating a methodology of SIMD unit Synthesis. Our system synthesizes a customized SIMD unit along with an extended instruction set and generates an equivalent version of assembly code for the application using the extended instruction set. The results of area and performance obtained by experimenting over our implementation of AltiVec compatible customized SIMD units show the effectiveness of our approach. |