| Thursday January 26, 2006 |
| Title | Delay Defect Screening for a 2.16GHz SPARC64 Microprocessor |
| Author | Noriyuki Ito, *Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi (Fujitsu Limited, Japan) |
| Page | pp. 342 - 347 |
| Keyword | microprocessor, delay fault, screening, at-speed |
| Abstract | This paper presents a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A non-robust delay test is used while each test vector is compacted to detect multiple transition faults in a standard scan-based design. Our test technique applied to a microprocessor designed with 6M gate logic, 4MB level 2 cache, and 239K latches, achieves 90% coverage using 3,103 test vectors. We show the correlation between the screening result and the actual number of delay defects. |
| Title | A Dynamic Test Compaction Procedure for High-quality Path Delay Testing |
| Author | Masayasu Fukunaga (Fujitsu Ltd., Japan), Seiji Kajihara, *Xiaoqing Wen (Kyushu Institute of Technology, Japan), Toshiyuki Maeda, Shuji Hamada, Yasuo Sato (Semiconductor Technology Academic Research Center, Japan) |
| Page | pp. 348 - 353 |
| Keyword | delay testing, test generation, test compaction, path delay fault |
| Abstract | We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set for selected faults, the generated test set would detect not only the selected faults but also faults on many unselected paths. Hence both high test quality by detecting untargeted faults and test cost reduction by reducing test patterns can be achieved. Experimental results show that the effectiveness of the proposed procedure. |
| Title | Delay Variation Tolerance for Domino Circuits |
| Author | Kai-Chiang Wu, *Cheng-Tao Hsieh, Shih-Chieh Chang (Department of CS, National Tsing Hua University, Taiwan) |
| Page | pp. 354 - 359 |
| Keyword | Delay variation, tolerance |
| Abstract | Factors of delay variation may cause a manufactured chip to violate the pre-specified timing constraint. In this paper, we propose a re-synthesis technique to tolerate delay variation for domino circuits. Note that the slacks of nodes along critical paths are zero; any delay addition to those zero-slack nodes will worsen the final performance of a circuit. Our basic idea is to increase the slacks of nodes in the critical region by appending a redundant auxiliary sub-circuit to the original circuit. |
| Title | Efficient Identification of Multi-Cycle False Path |
| Author | Kai Yang, *Tim Cheng (University of California, Santa Barbara, United States) |
| Page | pp. 360 - 365 |
| Keyword | false path, timing analysis, multi-cycle, sensitization, clock period |
| Abstract | In this paper, we address the timing analysis problem by considering both single-cycle and multi-cycle operations. We give a precise definition of multi-cycle false paths and provide the necessary conditions for multi-cycle sensitizable paths. We then propose an efficient algorithm to identify multi-cycle false paths. |
| Title | IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults |
| Author | *Katherine Shu-Min Li (Dept. of Electronics Engineering, National Chiao Tung University, Taiwan), Yao-Wen Chang (Dept. of Electronics Engineering & Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan), Chauchin Su (Dept. of Electronics Control, National Chiao Tung University, Taiwan), Chung-Len Lee (Dept. of Electronics Engineering, National Chiao Tung University, Taiwan), Jwu E Chen (Dept. of Electrical Engineering, National Central University, Taiwan) |
| Page | pp. 366 - 371 |
| Keyword | interconnect diagnosis, optimal diagnosability, delay fault, crosstalk fault, oscillation ring |
| Abstract | We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and crosstalk glitches. We analyze the diagnosability of an interconnect structure and propose a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm which achieves the optimal diagnosability. Two optimization techniques improve the efficiency and effectiveness of interconnect diagnosis. In all experiments, our method achieves 100% fault coverage and the optimal diagnosis resolution. |