| Title | Wire Sizing with Scattering Effect for Nanoscale Interconnection |
| Author | Sean X. Shi, *David Z. Pan (University of Texas at Austin, United States) |
| Page | pp. 503 - 508 |
| Keyword | scattering effect, wire sizing, nanoscale, interconnection model, wire shaping |
| Abstract | For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay significantly. Existing works on scattering effect are mostly performed using very complicated physics-based models, while the scattering impact on nanoscale VLSI interconnect and optimization have not been studied. In this paper, we first present a simple, closed-form scattering effect resistivity model based on extensive empirical studies on measurement data. Then we apply the proposed scattering model to revisit several classic wire sizing/shaping problems. Our experimental results show that if the scattering effect is ignored or characterized inaccurately beyond 65nm, the resulting interconnect optimization might be way off from the real optimal solution, e.g., up to 70% underestimation of the delay, or 20x oversizing. We also obtain the new closed-form wiresizing functions with consideration of scattering effects. |
| Title | Adaptive Admittance-based Conductor Meshing for Interconnect Analysis |
| Author | *Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan (Purdue University, United States) |
| Page | pp. 509 - 514 |
| Keyword | discretization, high-frequency effects, inductance extraction, simulation |
| Abstract | We present a new algorithm for discretizing interconnects, a step that is typically performed to account for the non-uniformity of current flow at high frequencies. The algorithm is based on an easily-computable measure that correlates well with the model accuracy. This measure is used to refine the discretization of interconnects in an adaptive scheme so as to systematically trade off computation against model accuracy. We apply the proposed
discretization technique on two classes of problems in the analysis of VLSI interconnects: simulation and frequency-dependent inductance extraction. Numerical results establish that with the interconnect discretizations generated by our algorithm, a reduction in simulation and
extraction times by a factor between three and seven can be realized with negligible sacrifice in model accuracy (< 1% error). |
| Title | Interconnect RL Extraction at a Single Representative Frequency |
| Author | *Akira Tsuchiya (Kyoto University, Japan), Masanori Hashimoto (Osaka University, Japan), Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 515 - 520 |
| Keyword | extraction, transmission-line |
| Abstract | This paper proposes a method to determine a single frequency for
interconnect RL extraction.
Resistance and inductance of interconnects depend on
frequency, and hence the extraction frequency strongly affects
the modeling accuracy of interconnects.
The proposed method determines an extraction frequency
based on the transfer characteristic of interconnects.
By choosing the frequency where the transfer characteristic becomes maximum,
the extracted RL values achieve the accurate modeling of the waveform.
We experimentally verify that the proposed method provides
accurate transition waveforms over various interconnect topologies. |
| Title | An Efficient Algorithm for 3-D Reluctance Extraction Considering High Frequency Effect |
| Author | *Mengsheng Zhang, Wenjian Yu (EDA Lab, Department of Computer Science & Technology, Tsinghua University, China), Yu Du (Synopsys Inc., United States), Zeyi Wang (EDA Lab, Department of Computer Science & Technology, Tsinghua University, China) |
| Page | pp. 521 - 526 |
| Keyword | reluctance extraction, VLSI interconnect, inductance |
| Abstract | As shown in literatures, partial reluctance based circuit analysis is efficient in capturing on-chip inductance effect, because the partial reluctance exhibits much better locality than partial inductance. However, most previous works on reluctance extraction did not take high frequency effect into account and were not efficient enough for 3-D complex structure. In this paper, a new reluctance extraction algorithm is proposed considering the high frequency effect. Numerical experiments demonstrate that our algorithm can handle complex 3-D interconnect structures while exhibiting high accuracy and a speed-up ratio of several tens to hundreds over FastHenry. |
| Title | Macromodelling Oscillators Using Krylov-Subspace Methods |
| Author | Xiaolue Lai, *Jaijeet Roychowdhury (University of Minnesota, United States) |
| Page | pp. 527 - 532 |
| Keyword | Oscillator, Macromodel, MOR, LTV |
| Abstract | We present an efficient method for automatically extracting unified amplitude/phase macromodels of arbitrary oscillators from their SPICE-level circuit descriptions. Such comprehensive oscillator macromodels are necessary
for accuracy when speeding up simulation of higher-level circuits/systems, such as PLLs, in which oscillators are embedded. Standard MOR techniques for linear time invariant (LTI) and varying (LTV) systems are not applicable to
oscillators on account of their fundamentally nonlinear phase behaviour. By employing a cancellation technique to deflate out the phase component, we restore the validity and efficacy of Krylov-subspace-based LTV MOR techniques for macromodelling oscillator amplitude responses. The nonlinear
phase response is re-incorporated into the macromodel after the amplitude components have been reduced. The resulting unified macromodels predict oscillator waveforms, in the presence of any kind of input or interference, at far
lower computational cost than full SPICE-level simulation, and with far greater accuracy compared to existing macromodels. |