|Title||A Routability Constrained Scan Chain Ordering Technique for Test Power Reduction|
|Author||*Xuan-Lun Huang (Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan), Jiun-Lang Huang (Dept. of Electrical Engineering, National Taiwan University, Taiwan)|
|Page||pp. 648 - 652|
|Keyword||design-for-testability, test power reduction, scan chain|
|Abstract||In this paper, we propose a novel scan-chain ordering
technique for test power optimization under user-specified
Compared to previous methods, our technique improves in that
(1) it allows the user to explicitly set the routing constraints,
(2) the achievable power reduction is much less sensitive to
the routing constraints.
The proposed method is applied to six industrial designs.
The achievable power reduction is in the range of 37-48% without
violating any user-specified routing constraint.|
|Title||FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction|
|Author||*Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda University, Japan)|
|Page||pp. 653 - 658|
|Keyword||DFT, multiscan, test channel, test data compression|
|Abstract||This paper proposes a new multiscan-based test input data compression technique by employing a Fan-out Compression Scan Architecture (FCSCAN) for test cost reduction. The basic idea of FCSCAN is to target the minority specified 1 or 0 bits (either 1 or 0) in scan slices for compression. Due to the low specified bit density in test cube set, FCSCAN can significantly reduce input test data volume and the number of required test channels so as to reduce test cost. The FCSCAN technique is easy to be implemented with small hardware overhead and does not need any special ATPG for test generation. In addition, based on the theoretical compression efficiency analysis, improved procedures are also proposed for the FCSCAN to achieve further compression. Experimental results on both benchmark circuits and one real industrial design indicate that drastic reduction in test cost can be indeed achieved.|
|Title||Compaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits|
|Author||*Yoshinobu Higami (Ehime University, Japan), Kewal K. Saluja (University of Wisconsin-Madison, United States), Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu (Ehime University, Japan)|
|Page||pp. 659 - 664|
|Keyword||Diagnosis, Test compaction, Combinational circuit, Sequential circuit|
|Abstract||Substantial attention is being paid to the fault diagnosis problem in recent test literature.
Yet, the compaction of test vectors for fault diagnosis is little explored.
The compaction of diagnostic test vectors must take care of all fault pairs that
need to be distinguished by a given test vector set.
Clearly, the number of fault pairs is much larger than the number of faults thus making
this problem very difficult and challenging.
The key contributions of this paper are: 1) to use techniques for reducing the size
of fault pairs to be considered at a time, 2) to use novel variants of the
fault distinguishing table method for combinational circuits and
reverse order restoration method for sequential circuits, and 3) to introduce heuristics to manage the space complexity of considering all fault pairs for large circuits.
Finally, the experimental results for ISCAS benchmark circuits are
presented to demonstrate the effectiveness of the proposed methods.|
|Title||Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability|
|Author||Ashish Goel (Purdue University, United States), Swarup Bhunia (Case Western Reserve University, United States), Hamid Mahmoodi (San Francisco State University, United States), *Kaushik Roy (Purdue University, United States)|
|Page||pp. 665 - 670|
|Keyword||soft error, flip-flop, Enhanced Scan|
|Abstract||With technology scaling, soft error resilience is becoming a major concern in circuit design. This paper presents a class of low-overhead flip-flops suitable for soft error detection and correction. The proposed design reuses logic elements typically available in a standard-cell implementation of a flip-flop to reduce hardware overhead. We demonstrate that the proposed flip-flops are also suitable for enhanced scan based delay fault testing, which allows arbitrary two-pattern test application for the best combinational path testability. The proposed flip-flops show an average power reduction of 16% and area improvement of 17% compared to the best alternative techniques with no additional delay overhead. |
|Title||A Memory Grouping Method for Sharing Memory BIST Logic|
|Author||*Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara (Nara Institute of Science and Technology, Japan)|
|Page||pp. 671 - 676|
|Keyword||memory, BIST, wrapper, sharing, scheduling|
|Abstract||With the increasing demand of rich functionality to be included in an SoC, the SoCs are designed with hundreds of small size memories of different sizes and frequencies. If the memory BIST logics were individually added to many different types of small-sized memory, the area overhead would be very large. To reduce the area overhead of memory BIST, memory BIST logic sharing is very important. This paper proposes a memory grouping method for memory BIST logic sharing. A memory grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results show that the proposed method reduces up to 40.55% area of memory BIST wrapper. It is shown that selection from two types of connection methods is able to reduce more areas than using single connection method.|