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1C: Advances in High-Frequency and High-Speed Circuit Design and CAD
1C-1
| Title | A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates |
| Author | Xiren Wang, *Wenjian Yu, Zeyi Wang (Tsinghua University, China) |
| Abstract | The couplings via realistic lossy substrates can be modeled as frequency-dependent coupling parameters. The fast extraction at multiple frequencies can be accomplished in two sequent steps. The first is to extract the coupling resistance using a direct boundary element method (DBEM). The second is to revise the resistance into the parameter at the frequency in an exact and rapid way. The first step is time-consuming, while it runs only one time; the second repeats at each frequency, but is much easier. For more frequency calculation, this method is more advanced. Numerical experiments illustrate that this method has high accuracy, and it can be hundreds of times faster than an advanced Green's function based method. Substrates with arbitrary doping profiles can also be easily handled, which is partly verified by experiment. |
| Slides (pdf file) | 1C-1 |
1C-2
| Title | Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers |
| Author | Arthur Nieuwoudt, Tamer Ragheb, *Yehia Massoud (Rice University, United States) |
| Abstract | In this paper, we present a systematic synthesis methodology for fully integrated wideband low noise amplifiers that simultaneously optimizes impedance matching, noise figure, and other performance parameters. Leveraging an accurate analytical model, we hierarchically couple global optimization techniques with local convex optimization methods to efficiently locate optimal wideband LNA circuits. The results indicate that the methodology yields significant improvement in key LNA design constraints over existing methodologies while achieving up to one order of magnitude speedup in computational performance. |
| Slides (pdf file) | 1C-2 |
1C-3
| Title | PLLSim - An Ultra Fast Bang-bang Phase Locked Loop Simulation Tool |
| Author | *Michael James Chan, Adam Postula (University of Queensland, Australia), Yong Ding (NanoSilicon Pty Ltd, Australia) |
| Abstract | This paper presents a simulation tool targeted specifically at bang-bang type phase locked loop systems. The aim of this simulator is to quickly and accurately predict important PLL transient characteristics such as capture range, locking time, and jitter. We present a behavioral model for bang-bang type PLLs, and show how application of this model in a simulator can speed up simulation time by four to five orders of magnitude. With this performance, Monte-Carlo simulation techniques become not only feasible, but convenient. The simulator also models the major non-idealities typical of phase locked loop systems. The accuracy of the simulator is confirmed via detailed analysis and comparison with Matlab Simulink based models. |
| Slides (pdf file) | 1C-3 |
1C-4
| Title | A Programmable Fully-Integrated GPS receiver in 0.18µm CMOS with Test Circuits |
| Author | Mahta Jenabi, *Noshin Riahi, Ali Fotowat-Ahmadi (Unistar Micro Technology Inc., Canada) |
| Abstract | A 0.18um single chip GPS receiver with 19.5 mA power consumption is implemented in 6.5 mm2. A serial input digital control with additional testing structure not adding more than 4% to the Si area are used to the actual RF circuits in case of problems minimizing the number of Si runs. |
| Slides (pdf file) | 1C-4 |
1C-5
| Title | Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches |
| Author | Swarup Bhunia, *Massood Tabib Azar, Daniel Saab (Case Western Reserve University, United States) |
| Abstract | In recent years, several alternative devices have been proposed to deal with inherent limitation of conventional CMOS devices in terms of scalability at nanometer scale geometry. The fabrication and integration cost of these devices, however, have been prohibitive and/or the devices do not allow smooth transition from the conventional design paradigm. To address some of these limitations, we have developed a new family of devices called “Complementary Nano Electro-Mechanical Switches” (CNEMS) using carbon nanotubes as active switching/latching elements. The basic structure of these devices consists of three co-planar carbon nanotubes arranged so that the central nanotube can touch the two side carbon nanotubes upon application of a voltage pulse between them. Owing to the unique properties of carbon nanotubes, these devices have very low leakage current, low operation voltages, and have built-in energy storage to reduce computation power, resulting in very low overall power dissipation. CNEMS have stable on-off state and latching mechanism for non-volatile memory-mode operation. Besides, the devices can be readily integrated in the same substrate as CMOS transistors with high integration densities - thus, allowing easy manufacturability and hybridization with conventional CMOS devices. In this paper, we present the properties of these devices and based on our analysis, we propose a reconfigurable computation framework using these devices. For the first time, we demonstrate that these devices are promising in dynamically reconfigurable instant-on system development with about 25X lower power dissipation. |
| Slides (pdf file) | 1C-5 |