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1D: University Design Contest
1D-1
| Title | A 1Tb/s 3W Inductive-Coupling Transceiver Chip |
| Author | *Noriyuki Miura, Tadahiro Kuroda (Keio University, Japan) |
| Abstract | A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30um in a layout area of 1mm^2. Bi-Phase Modulation is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing reduces crosstalk and channel pitch. The BER is lower than 10^-13 with 150ps timing margin. |
| Slides (pdf file) | 1D-1 |
1D-2
| Title | 22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors |
| Author | *Ahmet Oncu, B.B.M. Wasanthamala Badalawa, Tong Wang, Minoru Fujishima (The University of Tokyo, Japan) |
| Abstract | The pseudo-millimeter-wave ultra-wideband (UWB) is attractive for applications in short-range automotive radar systems using 22 to 29GHz in order to realize road safety and intelligent transportation. Although CMOS is suitable for the short-range radar since processing units can be implemented in the same chip with the UWB front-end building block, it is difficult to operate CMOS pulse generators at such a high frequency. To realize the pseudo-millimeter-wave band using CMOS, we have proposed a new pulse generator consisting of a series of delay cells and edge combiners with waveform shaping. As a result of measurement using 90nm CMOS technology, 1Gbps/bit pulses are successfully generated with a power consumption of 1.4mW at a supply voltage of 0.9V. This result will be the key technology for a one-chip short-range radar system. |
| Slides (pdf file) | 1D-2 |
1D-3
| Title | A 2.8-V Multibit Complex Bandpass Delta-Sigma AD Modulator in 0.18µm CMOS |
| Author | *Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi (Gunma University, Japan), Masao Hotta (Musashi Institute of Technology, Japan) |
| Abstract | A second-order multibit switched-capacitor(SC) complex bandpass Delta-Sigma AD modulator has been designed, fabricated and tested for application to low-IF receivers in wireless communication systems. We have employed two new algorithms there to improve the signal-to-noise-and-distortion (SNDR) of the modulator. (i) A complex bandpass filter with I, Q dynamic matching to reduce the mismatch influence between I, Q paths. As its by-product, the complex modulator can be divided into two separate parts without signal line crossing between the upper and lower paths. Therefore, the layout design of the modulator can be greatly simplified; (ii) A new complex bandpass Data-Weighted Averaging (DWA) algorithm is implemented to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy. Implemented in a 0.18-µm CMOS process and at 2.8V supply, the modulator achieves a measured peak SNDR of 64.5dB at 20MS/s with a signal bandwidth of 78kHz while dissipating 28.4mW and occupying an area of 1.82mm2. |
| Slides (pdf file) | 1D-3 |
1D-4
| Title | A Wideband CMOS LC-VCO Using Variable Inductor |
| Author | *Kazuma Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu (Tokyo Institute of Technology, Japan) |
| Abstract | This paper proposes a novel wide-range tunable CMOS voltage controlled oscillator (VCO). VCO uses an on-chip variable inductor and switched capacitors as variable elements. The VCO was fabricated using a standard 0.18 um CMOS process with five metal layers. The oscillation frequency can be tuned from 1.28 GHz to 2.75 GHz with tuning range of 72 %. |
| Slides (pdf file) | 1D-4 |
1D-5
| Title | Design of Active Substrate Noise Canceller using Power Suplly di/dt Detector |
| Author | *Taisuke Kazama, Toru Nakura (The University of Tokyo, Japan), Makoto Ikeda, Kunihiro Asada (VLSI Design and Education Center, The University of Tokyo, Japan) |
| Abstract | As the growing demand of mixed-signal designs as A/D, D/A and PLL integrated with large scale digital circuits, substrate noise becomes serious concern. On the other hand, the remedies using guard ring and decoupling capacitor do not have enough efficiency against high frequency noise due to their parasitic component. To suppress the impact of substrate noise, on-chip active noise cancelling technique using di/dt detector has been proposed. This paper introduces an exapmle design of feedforward active substrate noise canceling technique using multiple power supply di/dt detector and demonstrates the noise cancelling results by the measurement of 0.35 $\mu$m CMOS test chip. |
| Slides (pdf file) | 1D-5 |
1D-6
| Title | A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces |
| Author | *Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu (Inst. of Communications Engineering, NTHU, Taiwan), Shuo-Hung Hsu (Inst. of Electronics Engineering, NTHU, Taiwan) |
| Abstract | For the first time, we implemented a reconfigurable load-balanced TDM switch IC with SERDES interface circuits for high speed networking applications. An NxN TDM switch could be constructed recursively from the TDM switch IC to achieve switching capacity of hundred gigabits per second or higher. The TDM switch IC contained a digital 8x8 TDM switch core with 8B10B CODECs and analog SERDES I/O interfaces. In the I/O interfaces, eight 2.56/3.2Gbps dual-mode 16/20:1 SERDES with CML buffers were developed. The 16/20:1 instead of 8/10:1 serializer and deserializer were used to reduce the required operating frequency in the switch core by half. New half-rate architectures and all static CMOS gates were used in the 16/20:1 serializer and deserializer for the low power consumption. A wide-band CML I/O buffer with our patented PMOS active load scheme was developed. All implementation were based on the 0.18 µm CMOS technology. Our implementation showed a 20 Gbps switching capacity for the 8¡Á8 TDM switch IC. |
| Slides (pdf file) | 1D-6 |
1D-7
| Title | Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation |
| Author | *Satoshi Fukuda, Daisuke Kawazoe, Kenichi Okada, Kazuya Masu (Tokyo Institute of Technology, Japan) |
| Abstract | This paper proposes a reconfigurable low noise amplifier (LNA) to realize self compensation of performance. Power consamption and intermodulation are compensated by bias voltage of input transistor. By tuning the bias voltage according to the input signal, the proposed LNA achieves more than 33 dBm improvement in delta-IM3, and 87 % of power reduction is realized at 1.9 GHz as compared to an LNA with a fixed bias voltage. |
| Slides (pdf file) | 1D-7 |
1D-8
| Title | Pseudo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems |
| Author | *Chee Hong Ivan Lai, Minoru Fujishima (University of Tokyo, Japan) |
| Abstract | A low-power, fully integrated 20-26 GHz broadband up-conversion mixer implemented with on-chip Marchand baluns is demonstrated on 90nm CMOS technology in this paper. The baluns employ capacitive coupling between two metal layers and include slotted shields to reduce substrate losses. At 22.1 GHz, the integrated mixer achieves a conversion gain of 2 dB with a maximum power dissipation of only 11.1mW from a 1.2V dc power supply at LO power of 5 dBm. |
| Slides (pdf file) | 1D-8 |
1D-9
| Title | Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique |
| Author | Roel Pantonial, Md. Ashfaquzzaman Khan (Graduate School of Engineering, Tohoku University, Japan), *Naoto Miyamoto (New Industry Creation Hatchery Center, Tohoku University, Japan), Koji Kotani, Shigetoshi Sugawa (Graduate School of Engineering, Tohoku Un |
| Abstract | This paper reports the architecture and performance of Flexible Processor III (FP3), a novel multi-context dynamically reconfigurable FPGA (DRFPGA) designed and fabricated in 0.35um 2P3M CMOS technology. FP3 employs a newly developed shift register-type temporal communication module to reduce the critical path delay. Our experimental results brought out, for the first time, that there exists cases where the fastest speed was achieved when multi contexts were in use. |
| Slides (pdf file) | 1D-9 |
1D-10
| Title | Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes |
| Author | *Li-Chun Lin, Shih-Hao Ou (National Chiao Tung University, Taiwan), Tay-Jyi Lin (Industrial Technology Research Institute, Taiwan), Siang-Sen Deng, Chih-Wei Liu (National Chiao Tung University, Taiwan) |
| Abstract | The performance of single-issue RISC cores can be improved significantly with multi-issue architectures (i.e. superscalar or VLIW) by activating the parallel functional units concurrently. However, they suffer high complexity or huge code sizes. In this paper, we borrow some ideas from old vector machines and propose a novel DSP architecture with very compact codes. In our simulations, the DSP has comparable performance to a 5-issue VLIW core with identical computing resources. However, its code sizes are reduced by a factor of 8. The DSP core has been implemented in the TSMC 0.13um CMOS technology, where the operating frequency is 305MHz and the silicon area is 1.45×1.4 mm2 including 12KB on-chip memory. |
| Slides (pdf file) | 1D-10 |
1D-11
| Title | A Highly Integrated 8 mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16 MHz SoC Platform |
| Author | Huan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, Ping Chao, *Wei-Cheng Hung, Kai-Yuan Jan (National Tsing Hua University, Taiwan) |
| Abstract | We present a hardwired decoder prototype for H.264/AVC main profile video. Our design takes as its input compressed H.264/AVC bit-stream and produces as its output video frames ready for display. We wrap the decoder core with an AMBA-AHB bus interface and integrate it into a multimedia SoC platform. Several architectural innovations at both IP and system levels are proposed to achieve very high performance at very low operating frequency. Running at 16 MHz FPGA, the whole demo system is able to real-time decode CIF (352x288) video at 30 frames per second. Moreover, we take system cost into consideration such that only a single external SDRAM is needed and memory traffic minimized. |
| Slides (pdf file) | 1D-11 |
1D-12
| Title | Configurable AMBA On-Chip Real-Time Signal Tracer |
| Author | *Chung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang (Dept. of Computer Science & Engineering, National Sun Yat-Sen University, Taiwan) |
| Abstract | This paper purpose an embedded AMBA signal tracer for microprocessor-based SoC’s. This tracer provides five trace resolution modes that can perform a cycle-accurate or a transaction-based trace collection in an unlimited time. Also this tracer is implemented in a Soft-IP style. It provides four parameters for tracing configuration. The experimental results show that the bus tracer can reach a good compression ratio of 96%. |
| Slides (pdf file) | 1D-12 |
1D-13
| Title | Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic |
| Author | *Shoun Matsunaga, Takahiro Hanyu (Tohoku University, Japan), Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu (ROHM, Japan) |
| Abstract | A complementary ferroelectric-capacitor (CFC) logic-circuit style is proposed for a compact and standby-power-free content-addressable memory (CAM). Since the use of the CFC logic circuit in designing a CAM cell makes it possible to merge both logic and non-volatile storage elements into serially connected ferroelectric capacitors, the CAM becomes compact. The standby power of the CAM is completely eliminated because the supply voltage can be cut off with maintaining stored data in the CAM. The test chip is fabricated by using 0.35-um ferroelectric CMOS, and the basic behavior can be also measured. |
| Slides (pdf file) | 1D-13 |
1D-14
| Title | A Multi-Drop Transmission-Line Interconnect in Si LSI |
| Author | *Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu (Tokyo Institute of Technology, Japan) |
| Abstract | This paper proposes a branching method for on-chip transmission line interconnects, which can reduce delay and power of global interconnects. A 6-mm-long transmission line interconnect with a branch is fabricated by using 0.18um standard Si CMOS process, and the measurement result performs 4Gbps signal transmission. |
| Slides (pdf file) | 1D-14 |
1D-15
| Title | A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology |
| Author | *Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera (Kyoto University, Japan) |
| Abstract | An on-chip signaling system consists of a CML driver, a differential transmission-line and a CML receiver is fabricated. We developed an impedance-unmatched driver for power reduction. The impedance-unmatched driver reduces the tail current of the CML buffer by tuning the load resistance. The designed circuit achieves 3mm, 10Gbps/channel on-chip signal transmission and the impedance-unmatched driver saves the energy per bit by 21% compared with the conventional impedance-matched driver. |
| Slides (pdf file) | 1D-15 |
1D-16
| Title | A 90nm 8x16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations |
| Author | *Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto University, Japan) |
| Abstract | We have fabricated FPGA device with functionalities measuring within-die variations in a 90nm process. Measured variations are used to configure each device to maximize the operating frequency by allocationg critical paths in faster portions. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Placement opeimization using a simple model circuit reveals that performance of the circuit is enhanced by 4% in average. The yield is enhanced by 32% to the worst case. |
| Slides (pdf file) | 1D-16 |
1D-17
| Title | A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI |
| Author | *Minoru Watanabe, Fuminori Kobayashi (Kyushu Institute of Technology, Japan) |
| Abstract | A Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 $\mu m$ -- 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented. |
| Slides (pdf file) | 1D-17 |
1D-18
| Title | Low-Power High-Speed 180-nm CMOS Clock Drivers |
| Author | *Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi (Chuo University, Japan) |
| Abstract | The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were fabricated using 0.18-µm CMOS technology. The first and second stages of the driver consisted of a single inverter and m inverters, respectively, and the register array stage was constructed with N delay flip-flops (D-FFs). A single inverter in the second stage drove N/m D-FFs where N was fixed at 40 and m varied from 1 to 40. Minimum PT and tdT were 251 µW and 0.640 ns, respectively and were both obtained at an m of 8. These values were 48.6% and 29.4% of maximum PT and tdT, respectively. Simulated and measured results agreed well with these SPICE simulated results. |
| Slides (pdf file) | 1D-18 |