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2B: On Chip Communication Methodology
2B-1
| Title | Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems |
| Author | *Minje Jun, Kwanhu Bang (Yonsei University, Republic of Korea), Hyuk-Jun Lee (Cisco Systems Incorporated, United States), Naehyuck Chang (Seoul National University, Republic of Korea), Eui-Young Chung (Yonsei University, Republic of Korea) |
| Abstract | We present a bus arbitration scheme for soft real-time constrained embedded systems. Some masters in such systems are required to complete their work for given timing constraints, resulting in the satisfaction of system-level timing constraints. The computation time of each master is predictable, but it is not easy to predict its data transfer time since the communication architecture is mostly shared by several masters. Previous works solved this issue by minimizing the latencies of several latency-critical masters, but the side effect of these methods is that it can increase the latencies of other masters, hence they may violate the given timing constraints. Unlike previous works, our method uses the concept of “slack” in order to make the latency as close as its given constraint, resulting in the reduction of the side effect. The proposed arbitration scheme consists of bandwidth-conscious arbiter and scheduler. The arbiter can be any existing bandwidth-conscious arbiter and the scheduler implements the latency-awareness proposed in this paper. The scheduler is involved in the arbitration only when it observes a request whose slack is not sufficient for the given timing constraint. The experimental results show that our method outperforms the conventional round-robin arbiter by more than 100% in the best case in terms of the longest violated cycles. |
| Slides (pdf file) | 2B-1 |
2B-2
| Title | A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses |
| Author | *Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung University, Taiwan) |
| Abstract | On an SoC bus, contentions occur while different IP cores request the bus access at the same time. Hence an arbiter is mandatory to deal with the contention issue on a shared bus system. In different applications, IPs may have real-time and/or bandwidth requirements. It is very difficult to design an arbitration algorithm to simultaneously meet these two requirements. In this paper, we propose an innovative arbitration algorithm, RB_lottery, to meet both of the requirements. It can provide not only the hard real-time guarantee but also the precise bandwidth controllability. The experimental results show that RB_lottery outperforms several well-known existing arbitration algorithms. |
| Slides (pdf file) | 2B-2 |
2B-3
| Title | Communication Architecture Synthesis of Cascaded Bus Matrix |
| Author | *Junhee Yoo, Dongwook Lee (Seoul National University, Republic of Korea), Sungjoo Yoo (Samsung Electronics, Republic of Korea), Kiyoung Choi (Seoul National University, Republic of Korea) |
| Abstract | For high frequency on-chip communication architecture design, we propose cascaded bus matrix-based solutions. Due to the huge design space in cascaded bus matrix design, it is crucial to perform an efficient design space exploration. In our work, we present a simulated annealing-based design space exploration. For an efficient representation of bus topology, we propose an encoding method called traffic group encoding and apply it to AMBA3 AXI-based bus system design. |
| Slides (pdf file) | 2B-3 |
2B-4
| Title | Topology Exploration for Energy Efficient Intra-tile Communication |
| Author | *Jin Guo, Antonis Papanikolaou, Francky Catthoor (IMEC, Belgium) |
| Abstract | With the technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The segmented bus template is an energy efficient architecture style for the on-chip communication between the components. To achieve the minimum energy operation, the netlist topology of the segmented bus should however be optimized accordingly. In this paper we present a strategy for the definition of an energy optimal netlist for segmented buses. An initial floorplanning stage provides information about the eventual lengths of the interconnect wires and a subsequent exploration step defines the optimal topology for the communication architecture. We motivate that a star topology generated using the wire length prediction can be up to a factor 4 more energy efficient compared to standard linear bus topologies. |
| Slides (pdf file) | 2B-4 |
2B-5
| Title | Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms |
| Author | Krishnan Srinivasan, *Karam S. Chatha, Goran Konjevod (Arizona State University, United States) |
| Abstract | Network-on-Chip (NoC) architectures with optimized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multi-processor System-on-Chip (MPSoC) devices. The application specific NoC design problem takes as input the system-level floorplan of the computation architecture, characterized library of NoC components, and the communication performance requirements. The objective is to generate an optimized NoC topology, and routes for the communication traces on the architecture such that the performance requirements are satisfied and power consumption is minimized. The paper discusses a two stage automated approach consisting of i) core to router mapping, and ii) topology and route generation for design of custom NoC architectures. In particular it presents an optimal technique for core to router mapping (stage i), and a factor 2 approximation algorithm for custom topology generation (stage ii). The superior quality of the techniques is established by experimentation with benchmark applications, and comparisons with an optimal integer linear programming (ILP) based technique. |
| Slides (pdf file) | 2B-5 |