6A: Timing Modeling and Optimization


6A-1
Title Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains
Author Chuan Lin (Magma Design Automation Inc., United States), *Hai Zhou (Northwestern University, United States)
Abstract Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown that the full optimization potential of clock skew scheduling can be reliably implemented using a few skew domains. In this paper we present an optimal skew scheduling algorithm for sequential circuits with flip-flops. Given a finite set of prescribed skew domains, the algorithm finds a domain assignment for each flip-flop such that the clock period is minimized with possible delay padding. Experimental results validate the efficiency of our algorithm and show 17% improvement on average in clock period.
Slides (pdf file) 6A-1

6A-2
Title An Efficient Computation of Statistically Critical Sequential Paths Under Retiming
Author Mongkol Ekpanyapong (Intel Corporation, United States), Xin Zhao, *Sung Kyu Lim (Georgia Institute of Technology, United States)
Abstract In this paper we present the Statistical Retiming-based Timing Analysis (SRTA) algorithm. The goal is to compute the timing slack distribution for the nodes in the timing graph and identify the statistically critical paths under retiming, which are the paths with a high probability of becoming timing-critical after retiming. SRTA enables the designers to perform circuit optimization on these paths to reduce the probability of them becoming timing bottleneck if the circuit is retimed as a post-process. We provide a comparison among static timing analysis (= STA), statistical timing analysis (= SSTA), retiming-based timing analysis (= RTA), and our statistical retiming-based timing analysis (SRTA). Our results show that the placement optimization based on SRTA achieves the best performance results.
Slides (pdf file) 6A-2

6A-3
Title Fast Electrical Correction Using Resizing and Buffering
Author Shrirang Karandikar, *Charles J Alpert (IBM Austin Research Laboratory, United States), Mehmet Yildiz, Paul Villarrubia, Steve Quay, Tuhin Mahmud (IBM EDA, United States)
Abstract Current design methodologies are geared towards meeting different design criteria, such as delay, area or power. However, in order to correctly identify the critical parts of a circuit for optimization, the circuit has to be electrically clean -- i.e., slews on each pin have to be within certain limits, a gate cannot drive more than a certain amount of capacitance, etc. Thus far, this requirement has largely been ignored in the literature. Instead, existing methods which optimize delay are used to fix electrical violations. This leads to solutions that are unnecessarily expensive, and still leave violations that remain unfixed. There is therefore a need for an area-efficient strategy that targets the electrical state of a circuit and fixes all violations quickly. This paper explicitly defines ``electrical violations'' and presents a flexible approach (called EVE, the Electrical Violation Eliminator) for fixing these. Experimental results validate our approach.
Slides (pdf file) 6A-3

6A-4
Title SmartSmooth: A Linear Time Convexity Preserving Smoothing Algorithm for Numerically Convex Data with Application to VLSI Design
Author Sanghamitra Roy (University of Wisconsin-Madison, United States), *Charlie Chung-Ping Chen (National Taiwan University, Taiwan)
Abstract Convex optimization problems are very popular in the VLSI design society due to their guaranteed convergence to a global optimal point. While optimizing tabular data, significant fitting efforts are required to fit the data into convex form. Fitting the tables into analytically convex forms like posynomials, suffers from excessive fitting errors, as the fitting problem may be non-convex. In recent literature optimal numerically convex tables have been proposed. Since these tables are numerical, it is extremely important to make the table data smooth, and yet preserve its convexity. The smoothness ensures that the convex optimizer behaves predictably and converges quickly to the global optimal point. The existing smoothing techniques either cannot preserve convexity, or require very high execution time. In this paper, we propose a linear time algorithm to smoothen a given numerically convex data and at the same time preserve convexity. Our proposed algorithm SmartSmooth can smoothen the data in linear time without introducing any additional error on the numerically convex data. This algorithm can be a significant contribution in the field of optimization of non-analytical data. We present our SmartSmooth results on industrial cell libraries. SmartSmooth when applied on convex tables produced by ConvexFit shows a 30X reduction in fitting error over a posynomial fitting algorithm and 3X reduction in fitting error over ConvexSmooth algorithm.
Slides (pdf file) 6A-4

6A-5
Title Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies
Author *Zhangcai Huang, Hong Yu (The Graduate School of Information, Production and Systems, Waseda University, Japan), Atsushi Kurokawa (Sanyo Semiconductor Company, Japan), Yasuaki Inoue (The Graduate School of Information, Production and Systems, Waseda Unive
Abstract With the scaling of CMOS technology, the overshooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of the process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.
Slides (pdf file) 6A-5
Last Updated on: January 29, 2007