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7C: Test Cost Reduction Techniques
7C-1
| Title | Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores |
| Author | *Danella Zhao, Unni Chandran (University of Louisiana at Lafayette, United States), Hideo Fujiwara (Nara Institute of Science and Technology, Japan) |
| Abstract | This paper proposes a novel power-aware multi-frequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time and bandwidth are well handled by gating off certain virtual cores at a time while parallelizing the remaining. A shelf packing based optimization algorithm is proposed to design and optimize the wrapper architecture while minimizing the test time under power and bandwidth constraints |
| Slides (pdf file) | 7C-1 |
7C-2
| Title | Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses |
| Author | *Fawnizu Azmadi Hussin, Tomokazu Yoneda (Nara Institute of Science and Technology, Japan), Alex Orailoglu (University of California, San Diego, United States), Hideo Fujiwara (Nara Institute of Science and Technology, Japan) |
| Abstract | An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set of test configuration graphs, which are then used to determine the optimum test configurations and test delivery schedule under a given power constraint. In order to validate the effectiveness of the proposed methodology, a number of experiments are run on several modified benchmark circuits. The results clearly underscore the advantages of the proposed methodology. |
| Slides (pdf file) | 7C-2 |
7C-3
| Title | An Architecture for Combined Test Data Compression and Abort-on-Fail Test |
| Author | *Erik Larsson, Jon Persson (Linköpings Universitet, Sweden) |
| Abstract | The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (Multiple-Input Signature Register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X). |
| Slides (pdf file) | 7C-3 |
7C-4
| Title | RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power |
| Author | *Hao Fang, Chenguang Tong, Xu Cheng (Micro Processor Research and Development Center of Peking University, China) |
| Abstract | As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip(SoC), several compression coding schemes have been proposed. Extended frequency-directed run-length (EFDR) is one of the best coding compression schemes. In this paper, we present a novel algorithm named RunBasedReordering(RBR), which is based on EFDR codes. Three techniques have been applied to this algorithm: scan chain reordering, scan polarity adjustment and test pattern reordering. The experiment results show that the test data compression ratio is significantly improved and scan power consumption is dramatically reduced. Moreover, our algorithm can be easily integrated into the existing industrial flow with little area penalty. |
| Slides (pdf file) | 7C-4 |
7C-5
| Title | Systematic Scan Reconfiguration |
| Author | *Ahmad Al-Yamani (KFUPM, Saudi Arabia), Narendra Devta-Prasanna (University of Iowa, United States), Arun Gunda (LSI Logic, United States) |
| Abstract | We present a new test data compression technique that achieves 10x to 40x compression ratios without requiring any information from the ATPG tool about the unspecified bits. The technique is applied to both single-stuck as well as transition fault test sets. The technique allows aggressive parallelization of scan chains leading to similar reduction in test time. It also reduces tester pins requirements by similar ratios. The technique is implemented using a hardware overhead of a few gates per scan chain. |
| Slides (pdf file) | 7C-5 |