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8B: Electrical Optimization in Floorplanning/Placement
8B-1
| Title | Thermal-Aware 3D IC Placement Via Transformation |
| Author | Jason Cong, *Guojie Luo, Jie Wei, Yan Zhang (Department of Computer Science, University of California, Los Angeles, United States) |
| Abstract | 3D IC technologies can help to improve circuit performance, lower power consumption by reducing wirelength and realize heterogeneous system-on-chip design. In this paper, we propose a novel thermal-aware 3D cell placement approach, named T3Place, based on transforming a 2D placement with good wirelength to a 3D placement, with the objectives of wirelength, through-the-silicon (TS) via number and temperature. Moreover, we proposed a novel relaxed conflict-net (RCN) graph-based layer assignment method to further refine the 3D placements. |
| Slides (pdf file) | 8B-1 |
8B-2
| Title | Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling |
| Author | Fayez Mohamood, Michael Healy, Sung Kyu Lim, *Hsien-Hsin S. Lee (Georgia Tech, United States) |
| Abstract | This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement to tackle high-frequency inductive noise. Given the increasing use of clock-gating for saving power, reliability has been worsened by induced large inductive noise. In this work, we propose an average-case design method by considering the dynamic microarchitectural switching behavior to guarantee power integrity and alleviate the requirement of on-die decoupling capacitances. |
| Slides (pdf file) | 8B-2 |
8B-3
| Title | On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design |
| Author | *Chao-Hung Lu (National Central University, Taiwan), Hung-Ming Chen (National Chiao Tung University, Taiwan), Chien-Nan Jimmy Liu (National Central University, Taiwan) |
| Abstract | With technology further scaling into deep submicron era, more components can be placed onto one chip (System-on-chip, SoC). However, the same scaling brings the design difficulties, among which signal integrity is one of the most important issues. Although flip-chip and area-array architectures have been proposed to strengthen the integrity, we still need careful planning in SoC designs. Power supply noise problem is getting worse due to serious IR-drop and simultaneous switching noise, and decoupling capacitance (decap) insertion is commonly applied to alleviate the noise. There exist some approaches to addressing this issue, but they suffer either from over-design problem or late decap insertion during design stage. In this paper, we propose a methodology to insert decap in a more efficient and effective way during supply noise driven floorplanning in area-array designs. The experimental results are encouraging. Compared with other approaches in \cite{Koh} and \cite{Yan}, we have inserted enough decap to meet supply noise constraint while others employ more area. |
| Slides (pdf file) | 8B-3 |
8B-4
| Title | Voltage Island Generation under Performance Requirement for SoC Designs |
| Author | *Wai-Kei Mak, Jr-Wei Chen (National Tsing Hua University, Taiwan) |
| Abstract | Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we just set the cores to operate at their respective lowest voltage levels. We present two formulations for the voltage level assignment problem. The first is exact but takes longer time to compute a solution. The second can be solved much faster with virtually no loss on optimality. In addition, we propose a modification to the traditional floorplanning framework. Unlike previous works, we can optimize the total power consumption, the level shifter overhead, and the power network complexity without com- promising the wirelength and the chip area. In the experiments, we obtained 17- 53% power savings with voltage island generation. |
| Slides (pdf file) | 8B-4 |
8B-5
| Title | Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign |
| Author | *Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen (National Chiao Tung University, Taiwan) |
| Abstract | Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface design has been a time-consuming process. This paper proposes a novel and efficient approach to designating pinout for flip-chip BGA package when designing chipsets. The proposed approach can not only automate the assignment of more than 200 I/O pins on package, but also precisely evaluate package size which accommodates all pins with almost no void pin positions, as good as the one from manual design. Furthermore, the practical experience and techniques in designing such interface has been accounted for, including signal integrity, power delivery and routability. This efficient pin-out designation and package size estimation by pin-block design and floorplanning provides much faster turn around time, thus enormous improvement in meeting design schedule. The results on two real cases show that our methodology is effective in achieving almost the same dimensions in package size, compared with manual design in weeks, while simultaneously considering critical issues in package-board codesign. To the best of our knowledge, this is the first attempt in solving flip-chip pin-out placement problem in package-board codesign. |
| Slides (pdf file) | 8B-5 |