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8D: Designers' Forum - High-speed Chip to Chip Signaling Solutions
8D-1
| Title | Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation |
| Author | *Atsushi Hiraishi, Toshio Sugano (Elpida Memory, Japan), Hideki Kusamitsu (Yamaichi Electronics, Japan) |
| Abstract | In this paper we showed the signal degradation parts in High-speed channel of FB-DiMM system. And we also showed possible countermeasure. For the verification propose and also for establishing the precise modeling and simulation method, we compared measurement and simulation up to 9.6Gbps operation with test board. And we get good relation between them. After getting the calculated loss budget of estimated system, we made recommendations of preferable changes to Main board and DiMM socket. |
| Slides (pdf file) | 8D-1 |
8D-2
| Title | Xbox360(TM) Front Side Bus - A 21.6 Gb/s End to End Interface Design |
| Author | *David Siljenberg, Steve Baumgartner, Tim Buchholtz, Mark Maxson, Trevor Timpane (IBM, United States), Jeff Johnson (Cadence Design Systems, United States) |
| Abstract | With a bandwidth of 21.6 GB/s, the Front Side Bus (FSB) of the Microsoft Xbox360TM is one of the fastest, commercially available Front Side Bus interfaces in the consumer market. This paper explains the end-to-end system approach used in designing the bus that achieved volume production ramp 18 months after design start. The 90 nm SOI-CMOS CPU and 90 nm bulk CMOS GPU designs are described. The chip carrier, circuit board, and signal integrity analyses are described. The design approach used to achieve high volume, low cost, and short development time is explained. |
| Slides (pdf file) | 8D-2 |
8D-3
| Title | Design Consideration of 6.25 Gbps Signaling for High-Performance Server |
| Author | *Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone (Fujitsu Laboratories of America, United States) |
| Abstract | As network data rate increases rapidly, high-speed signaling circuits for server communication pose many design challenges due to various system requirements using different interconnect mediums. This paper discusses main problems and solutions of high-speed circuits for server interconnect. Then, it presents a high-speed circuit implementation for such interconnect using 90nm CMOS technology that achieved data rate at 6.25 Gbps in a backplane environment. |
| Slides (pdf file) | 8D-3 |
8D-4
| Title | System Co-Design and Co-Analysis Approach to Implementing the XDR(TM) Memory System of the Cell Broadband EngineTM Processor Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production |
| Author | *Wai-Yeung Yip, Scott Best, Wendemagegnehu Beyene, Ralf Schmitt (Rambus, United States) |
| Abstract | This paper describes the design and analysis of the 3.2 Gbps XDR(TM) memory system of the Cell Broadband Engine(TM) (Cell BE) processor developed by Sony Corporation, Sony Computer Entertainment, Toshiba and IBM. A System Co-Design and Co-Analysis Approach was applied where different components of the system are designed and analyzed simultaneously to allow trade-offs to be made to optimize system electrical characteristics at low overall system cost. The XDR memory interface circuit implemented in the Cell BE processor, the power delivery system design and analysis, and the interface statistical signal integrity analysis will be described to illustrate this design and analysis approach. |
| Slides (pdf file) | 8D-4 |