9A: Power Efficient Design Techniques


9A-1
Title Flow Time Minimization under Energy Constraints
Author *Jian-Jia Chen (National Taiwan University, Taiwan), Kazuo Iwama (Kyoto University, Japan), Tei-Wei Kuo, Hseuh-I Lu (National Taiwan University, Taiwan)
Abstract Power-aware and energy-efficient designs play important roles for modern hardware and software designs, especially for embedded systems. This paper targets a scheduling problem on a processor with the capability of dynamic voltage scaling (DVS), which could reduce the power consumption by slowing down the processor speed. The objective of the targeting problem is to minimize the average flow time of a set of jobs under a given energy constraint, where the flow time of a job is defined as the interval length between the arrival and the completion of the job. We consider two types of processors, which have a continuous spectrum of the available speeds or have only a finite number of discrete speeds. Two algorithms are given: (1) An algorithm is proposed to derive optimal solutions for processors with a continuous spectrum of the available speeds. (2) A greedy algorithm is designed for the derivation of optimal solutions for processors with a finite number of discrete speeds. The proposed algorithms are extended to cope with jobs with different weights for the minimization of the average weighted flow time. The proposed algorithms are also evaluated with comparisons to schedules which execute jobs at a common effective speed.
Slides (pdf file) 9A-1

9A-2
Title Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost
Author Bita Gorjiara, Nader Bagherzadeh, *Pai Chou (University of California, Irvine, United States)
Abstract The development cost of low-power embedded systems can be reduced by reusing legacy designs and applying proper modifications to meet power constraints. The power management techniques for implementing distributed power managers in multi-processor systems, are very costly in terms of hardware/software modifications. In this paper, we propose a new centralized power management technique that reduces the power consumption of distributed systems at very low implementation cost. Our power manager uses the model of the system/application to compute the schedule of turn on/off commands. We applied our power management technique to a distributed software-defined radio system and achieved 60% to 87% energy savings.
Slides (pdf file) 9A-2

9A-3
Title A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
Author *Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura (Kyushu University, Japan)
Abstract Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may even change position with changes in the operating voltage and temperature, and hence, redundancy at circuit-level is not sufficient to tolerate such threats to yield. We show that in SRAM cells this leakage depends on the cell value and propose a first software-based runtime technique that suppresses such abnormal leakages by storing safe values in the corresponding cache lines before going to standby mode. Analysis shows the performance penalty is, in the worst case, linearly dependent to the number of so-cured cache lines while the energy saving linearly increases by the time spent in standby mode. Analysis and experimental results on commercial processors confirm that the technique is viable if the standby duration is more than a small fraction of a second.
Slides (pdf file) 9A-3

9A-4
Title Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency
Author *Subhasis Banerjee (Sun Microsystems, India), Surendra G, S. K. Nandy (Indian Institute of Science, India)
Abstract Aggressive superscalar processor with deep pipeline and sophisticated speculative execution techniques is pushing the power budget to its limit. It is found that a significant portion of this power is wasted during wrong path execution and non power optimal allocation of power hungry resources. Dynamic reconfiguration of micro-architectural resources can be exploited to bring down this waste at runtime. Lack of architectural method to capture the behavior of a program at runtime makes dynamic reconfiguration a challenge. In this paper we propose a method to characterize program behavior at runtime using conflict miss pattern of a data cache, which in turn identifies different program phases in terms of cache utilization. We use this phase information to enable/disable cache ways dynamically depending on the conflict miss pattern of a program. Using a hardware tracking mechanism we ensure that the program performance (throughput in terms of IPC) does not degrade beyond a tolerable limit.
Slides (pdf file) 9A-4

9A-5
Title CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time
Author *Jorgen Peddersen, Sri Parameswaran (University of New South Wales, Australia)
Abstract Numerous dynamic power management techniques have been proposed which utilize the knowledge of processor power/energy consumption at run-time. So far, no efficient method to provide run-time power/energy data has been presented. Current measurement systems draw too much power to be used in small embedded designs and existing performance counters can not provide sufficient information for run-time optimization. This paper presents a novel methodology to solve the problem of run-time power optimization by designing a processor that estimates its own power/energy consumption. Estimation is performed by the addition of small counters that tally events which consume power. This methodology has been applied to an existing processor resulting in an average power error of 2% and energy estimation error of 1.5%. The system adds little impact to the design, with only a 4.9% increase in chip area and a 3% increase in average power consumption. A case study of an application that utilizes the processor showcases the benefits the methodology enables in dynamic power optimization.
Slides (pdf file) 9A-5
Last Updated on: January 29, 2007