Preparation Guide for Technical Paper Submission

New Deadline

The new deadline for technical papers is July 11 (Tue), 2006 (9:00 am JST). CLOSED
** This deadline is HARD. No more extensions will be given. **

The deadline by local times is as follows:

  • July 10 17:00 @ San Jose
  • July 10 20:00 @ New York
  • July 11 1:00 @ London
  • July 11 2:00 @ Paris, Munich
  • July 11 5:30 @ New Delhi
  • July 11 8:00 @ Beijing, Taipei
  • July 11 9:00 @ Tokyo, Seoul
  • July 11 10:00 @ Sydney

Key Dates:

  • Deadline for submission: July 10 (Mon), 2006 (17:00, JST) July 11 (Tue), 2006 (9:00 am JST)
  • Notification of acceptance: September 29 (Fri), 2006
  • Deadline for final version: November 17 (Fri), 2006

Instructions

In order to submit your paper, please follow the instructions below.

1) Paper preparation

  • Initial manuscripts should NOT include authors' names and their affiliations in order to perform a blind review. Authors' names, their affiliations and the contact person are requested when you submit your paper via the paper submission system.


  • The paper should be between 3 to 6 pages in length including all figures, tables and references. The technical expositions will be reviewed by specialists but should include an introduction for nonspecialists that describes the problem and achieved results, focusing on the important ideas and their significance.


  • Accepted file format is PDF only. No other formats will be accepted. You must make a pdf file which can be read by Acrobat Reader 5.0. Manuscripts should not include special fonts such as Asian fonts.


  • The paper for initial submission is to be formated like this (LaTex, LaTex2e). You can get the templates of initial sumission for (LaTex), (LaTex2e), and (MSWord).


2) Paper Submission

  • Please submit the manuscript via the paper submission system (CLOSED).

Requirement

  • All accepted papers should be presented at the conference.
  • Dual submission with other conferences is not allowed.

Remarks:

  • Papers will be accepted for publication as either of regular papers or short papers. The paper type ** cannot ** be chosen by authors when submitting papers.
  • Papers may need to be shortened after acceptance, depending on the paper type. The page limit for short papers will be four.
  • The page limit for regular papers is 6 pages. For the camera-ready version up to 2 extra pages (maximum 8 pages) are allowed with extra payment.
  • Any modification in authors' names including the order of the listed authors after submission deadline is not allowed except that TPC approves the modification.


Area of Interest:

Original, unpublished works on, but not limited to, the following areas are invited.

[1] System Level Design:
System VLSI and SOC design methods, System specification, Specification languages, Design languages, Design reuse and IPs, Tools/methods for low power system design, Platform-based design, Network on chip design
[2] Embedded and Real-Time Systems:
Hardware-software co-design, Co-simulation, Co-verification, Real-time OS and middleware, Design language for embedded systems, Compilation techniques, ASIP synthesis
[3] Behavioral/Logic Synthesis and Optimization:
Behavioral/RTL synthesis, Technology independent optimization, Technology mapping, Interaction between logic design and layout, Sequential and asynchronous logic synthesis
[4] Validation and Verification for Behavioral/Logic Design:
Logic simulation, Symbolic simulation, Formal verification, Equivalence checking, Transaction-level/RTL and gate level modeling and validation
[5] Physical Design (Routing):
Routing, Repeater issues, Interconnect optimization, Interconnect planning, Module generation, Layout verification
[6] Physical Design (Placement):
Placement, Floorplanning, Partitioning, Hierarchical design
[7] Timing, Power, Signal/Power Integrity Analysis and Optimization:
Timing analysis, Power analysis, Signal/power integrity, Clock and global signal design
[8] Interconnect, Device and Circuit Modeling and Simulation:
Interconnect modeling, Interconnect extraction, Package modeling, Circuit simulation, Device modeling/simulation, Library design, Design fabrics, Design for manufacturability, Yield optimization, Reliability analysis, Emerging technologies
[9] Test and Design for Testability:
Test design, Fault modeling, ATPG, BIST and DFT, Memory, core and system test
[10] Analog, RF and Mixed Signal Design and CAD:
Analog/RF synthesis, Analog layout, Verification, Simulation techniques, Noise analysis, Analog circuit testing, Mixed signal design
[11] Leading Edge Design Methodology for SOCs and SIPs:
Design methodology for Microprocessors, DSP, IP-core, multimedia processors, wireless communication systems, A/D mixed circuits, Memories, Sensors, MEMS chips, FPGAs, Novel reconfigurable systems, Rapid prototyping

*Please note that ASP-DAC 2007 University LSI Design Contest encourages original papers on LSI design and implementation at universities and other educational organizations.

Inquiry

For more information, please contact: aspdac07papers@slrc.kyushu-u.ac.jp

Technical Program Chair
Yusuke Matsunaga

Technical Program Vice Co-Chairs
Kiyoung Choi
Youn-Long Lin

Last Updated on: 7 9, 2006