Highlights

	Keynote Addresses
	Opening & Keynote I : Wednesday, January 24, 8:30-10:00, Small Auditorium, 5F Next-generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Toolchains Rob A. Rutenbar Electrical & Computer Engineering, Carnegie Mellon University, United States
	Keynote II : Thursday, January 25, 9:00-10:00, Small Auditorium, 5F Meeting with the Forthcoming IC Design - The Era of Power, Variability and NRE Explosion and a Bit of the Future - Takayasu Sakurai Center for Collaborative Research, and Institute of Industrial Science, University of Tokyo, Japan
	Keynote III : Friday, January 26, 9:00-10:00, Small Auditorium, 5F How Foundry can Help Improve your Bottomline? Accuracy Matters! Fu-Chieh Hsu Vice President of Design and Technology Platform, Taiwan Semiconductor Manufacturing Company, Taiwan

	Special Sessions
	1D : Wednesday, January 24, 10:15-12:20, Room 416+417, 4F Presentation + Poster Discussion: University Design Contest
	2D : Wednesday, January 24, 13:30-15:35, Room 416+417, 4F Invited Talks + Panel Discussion: Design for Manufacturability
	3D : Wednesday, January 24, 16:00-18:05, Room 416+417, 4F Invited Talks: Embedded Software for Multiprocessor Systems-on-Chip
	4D : Thursday, January 25, 10:15-12:20, Room 416+417, 4F Invited Talks: EDA Challenges for Analog/RF
	7D : Friday, January 26, 10:15-12:20, Room 416+417, 4F Panel Disucssion: Multi-Processor Platforms for Next Generation Embedded Systems

	Designers' Forum
	5D : Thursday, January 25, 13:30-15:35, Small Auditorium, 5F Panel Discussion: Presilicon SoC HW/SW Verification
	6D: Thursday, January 25, 16:30-17:50, Small Auditorium, 5F Invited Talks: Low-power SoC Technologies
	8D: Friday, January 26, 13:30-15:35, Small Auditorium, 5F Invited Talks: High-speed Chip to Chip Signaling Solutions
	9D: Friday, January 26, 16:30-18:05, Small Auditorium, 5F Panel Disussion: Top 10 Design Issues

	Tutorials
	Tutorial 1 (Full Day) : Tuesday, January 23, 9.30-17.00, Room 411+412, 4F DFM Tools and Methodologies at 65nm and Beyond
	Tutorial 2 (Full Day) : Tuesday, January 23, 9.30-17.00, Room 413, 4F Functional Verification Planning and Management - The Road to Verification Closure is Paved with Good Intentions
	Tutorial 3 (Half Day) : Tuesday, January 23, 9.30-12.30, Room 414+415, 4F Low Power CMOS Design: The Fabrics: Research Front-End
	Tutorial 4 (Half Day) : Tuesday, January 23, 14.00-17.00, Room 414+415, 4F Low Power CMOS Design: The Applications: State-of-the-Art Practice
	Tutorial 5 (Half Day) : Tuesday, January 23, 9.30-12.30, Room 416+417, 4F Fast Physical Synthesis for Multi-Million Gate ASIC Designs
	Tutorial 6 (Half Day) : Tuesday, January 23, 14.00-17.00, Room 416+417, 4F Concepts and Tools for Practical Embedded System Design

Last Updated on: October 30, 2006