Sponsored By:
デザイナーズ・フォーラム
デザイナーズフォーラムは，設計に関する経験と業界における現実の製品設計に関するソリューションを共有するための新しいプログラムです．今回のトピックは SoC HW/SW検証，SoCのための低消費電力技術，チップ間信号伝達問題，LSI設計の10大課題です．
- 日時：2007年1月25-26日
- 場所: パシフィコ横浜、コンファレンス・センター、小ホール5F
- Designers' Forum Chair, Industry Liaison Chair: Haruyuki Tago (TOSHIBA CORPORATION)
- Designers' Forum Vice Chair: Kazutoshi Kobayashi (Kyoto University)
- Industry Liaison
| Date/Time | Title | ||
| 5D | 1月25日/ 13:30 - 15:35 | パネル討論: SoCのハードソフト協調検証 |
|
| 6D | 1月25日 / 16:00 - 17:50 | 招待講演: SoCのための低消費電力技術 |
|
| 8D | 1月26日 / 13:30 - 15:35 | 招待講演: チップ間高速信号伝送技術 |
|
| 9D | 1月26日 / 16:00 - 18:05 | パネル討論: LSI設計の10大課題 |
5D : Thursday, January 25, 13:30-15:35, Small Auditorium, 5F
Panel Discussion : Presilicon SoC HW/SW Verification
(パネル討論: SoCのハードソフト協調検証)
Organizer: Tetsuji Sumioka (Sony, Japan)
Moderator: Tetsuji Sumioka (Sony, Japan)
Panelists: Jason Andrews (Cadence, United States),
Graham Hellestrand (VaST Systems Technology, United States),
Hidefumi Kurokawa (NEC Electronics, Japan),
Ilya Klebanov (Advanced Micro Devices, Canada),
Seiji Koino (Toshiba, Japan)
6D: Thursday, January 25, 16:00-17:50, Small Auditorium, 5F
Invited Talks: Low-power SoC Technologies
(招待講演 : SoC のための低消費電力技術)
6D-1: Plenary Talk --Overview on Low Power SoC Design Technology--
Kimiyoshi Usami (Shibaura Inst. of Tech., Japan)
6D-2: The Development of Low-power and Real-time VC- 1/H.264/MPEG-4 Video Processing Hardware
Masaru Hase, Kazushi Akie, Masaki Nobori, Keisuke Matsumoto (Renesas, Japan)
6D-3: Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-media Engine SoC (S1G)
Koichi Mori, Masakazu Suzuki, Yasuo Ohara, Satoru Matsuo, Atsushi Asano (Toshiba, Japan)
6D-4: Low Power Techniques for Mobile Application SoCs based on Integrated Platform “UniPhier”
Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita (Matsushita Electric Industrial, Japan)
8D: Friday, January 26, 13:30-15:35, Small Auditorium, 5F
Invited Talks: High-speed Chip to Chip Signaling Solutions
(招待講演: チップ間高速信号伝送技術)
8D-1: Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation
Atsushi Hiraishi, Toshio Sugano (Elpida Memory, Japan), Hideki Kusamitsu (Yamaichi Electronics)
8D-2:Xbox360TM Front Side Bus - A 21.6 Gb/s End to End Interface Design
David Siljenberg, Steve Baumgartner, Tim Buchholtz, Mark Maxson, Trevor Timpane (IBM, United States), Jeff Johnson (Cadence Design Systems, United States)
8D-3:Design Consideration of 6.25 Gbps Signaling for High-Performance Server
Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone (Fujitsu Laboratories of America, United States)
8D-4:System Co-design and Analysis Approach to Implementing the XDRTM Memory System of the Cell Processor Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production
Wai-Yeung Yip, Scott Best, Wendemagegnehu Beyene, Ralf Schmitt (Rambus, United States)
9D: Friday, January 26, 16:00-18:05, Small Auditorium, 5F
Panel Disussion: Top 10 Design Issues
(パネル討論: LSI設計の10大課題)
Organizer: Haruyuki Tago (Toshiba, Japan)
Moderator: Peter Hofstee (IBM, United States)
Panelists: Toshihiro Hattori(Renesas Technology, Japan)
Tadahiro Kuroda (Keio University, Japan)
Toshinari Takayanagi (P.A., Semi, United States)
Toshinori Sato (Kyushu University, Japan)