|Title||Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process|
|Author||*Subarna Sinha, Jianfeng Luo, Charles Chiang (Synopsys, United States)|
|Page||pp. 1 - 6|
|Abstract||Thickness range, i.e. the difference between the highest point and the
lowest point of the chip surface, is a key indicator of chip yield.
This paper presents a novel metal filling algorithm that seeks to
minimize the thickness range of the chip surface during the copper damascene process. The proposed solution considers the physical mechanisms in the damascene process, namely ECP (which is the process used to deposit Cu in the trenches) and CMP (which is the process used to polish Cu after ECP), that affect thickness range. Key predictors for the final thickness range, which is the thickness range after ECP & CMP, that can be computed efficiently are identified and
used to drive the metal filling process.
To the best of our knowledge, this is the first metal filling algorithm that uses an ECP model among other things to guide metal filling. Experimental results are very promising and indicate that the proposed method can significantly reduce the thickness range after metal filling. This is in sharp contrast with the density-driven approaches which often increase the thickness range after metal filling, thereby potentially adversely impacting yield. In addition, the proposed method inserts significantly smaller amount of fill when compared to the density-driven approaches. This is desirable as it limits the impact of metal filling on timing.|
|Title||Fast and Accurate OPC for Standard-Cell Layouts|
|Author||*David M. Pawlowski, Liang Deng, Martin D. F. Wong (University of Illinois at Urbana-Champaign, United States)|
|Page||pp. 7 - 12|
|Keyword||OPC, cell-wise, boundary-based, RET|
|Abstract||Model based optical proximity correction (OPC) has become necessary at 90nm technology node and beyond. Cellwise OPC is an attractive technique to reduce the mask data size as well as the prohibitive runtime of full-chip OPC. As feature dimensions have gotten smaller, the radius of influence for edge features has extended further into neighboring cells such that it is no longer sufficient at 65nm node and below to perform cellwise OPC independent of neighboring cells, especially for the metal layers. The methodology described in this work accounts for features in neighboring cells and allows a cellwise approach to be applied to cells with gate length of 45nm with the projection that it can also be applied to future technology nodes. OPC-ready cells are generated before placement using boundary-based technology. Each cell has a small number of OPC-ready versions due to an intelligent characterization of standard cell layout features. Total number of cells with boundaries in the OPC-ready library only increases linearly with the number of cells in the original library. Results are very promising: the average edge placement error (EPE) for all metal1 features in 100 layouts is 0.731nm which is less than 1% of metal1 width (80nm), creating similar levels of lithographic accuracy while obviating any of the drawbacks inherent in layout specific full-chip model-based OPC. For even small circuits, we got up to 100X runtime reduction and 35X mask data size shrinking.|
|Title||Coupling-aware Dummy Metal Insertion for Lithography|
|Author||*Liang Deng (University of Illinois at Urbana-Champaign, United States), Kaiyuan Chao (Intel Co., United States), Hua Xiang (IBM T.J. Watson Research Center, United States), Martin D. F. Wong (University of Illinois at Urbana-Champaign, United States)|
|Page||pp. 13 - 18|
|Keyword||dummy metal, lithography, coupling capacitance, RET|
|Abstract||As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip design. The widely used RET called off-axis illumination (OAI) introduces forbidden pitches which lead to very complex design rules. It has been observed that imposing uniformity on layout designs can substantially improve printability under OAI. For metal layers, uniformity can be achieved simply by inserting dummy metal wire segments at all free spaces. Simulation results indeed show significant improvement in printability with such a dummy metal insertion approach. To minimize mask cost, it is advantageous to use dummy metal segments that are of the same size as regular metal wires due to their simple geometry. But these dummy wires are printable and hence increase coupling capacitances and potentially affect yield. The alternative is to use a set of parallel sub-resolution thin wires (which will not be printed) to replace a printable dummy wire segment. These invisible dummy metal segments do not increase coupling capacitances but increase lithography cost, which includes mask cost and RET/process expense. This paper presents a strategy for dummy metal insertion that can optimally trade off lithography cost and coupling capacitance. In particular, we present an optimal algorithm that can minimize lithography cost subject to any given coupling capacitance bound. Moreover, this dummy metal insertion will achieve a highly uniform density because of the locality of coupling capacitance, which automatically ameliorates chemical mechanical polish (CMP) problem.|
|Title||Fast Buffer Insertion for Yield Optimization under Process Variations|
|Author||Ruiming Chen, *Hai Zhou (Northwestern University, United States)|
|Page||pp. 19 - 24|
|Keyword||buffer insertion, yield optimization|
|Abstract||With the emerging process variations in fabrication, the traditional corner-based timing optimization techniques become prohibitive. Buffer insertion is a very useful technique for timing optimization. In this paper, we propose a buffer insertion algorithm with the consideration of process variations. We use the solutions from the deterministic buffering that sets all the random variables at their nominal values to guide the statistical buffering algorithm.
Our algorithm keeps the sizes of solution lists small, and always achieves higher yield than the deterministic buffering.
The experimental results demonstrate that the exiting approaches cannot handle large cases efficiently or effectively, while our algorithm handles large cases very efficiently, and improves the yield more than 12\% on average. |
|Title||A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield|
|Author||*Bao Liu, Andrew Kahng, Xu Xu (University of California, San Diego, United States), Jiang Hu, Ganesh Venkataraman (Texas A&M University, United States)|
|Page||pp. 25 - 31|
|Keyword||clock, distribution, robust , design|
|Abstract||Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we proposeminimum clock distribution network augmentation for guaranteed skew yield. We present theoretical analysis results on an inserted link in a clock network, which scales down local skew and skew variation, but may not guarantee global skew and skew variation reduction in general. We propose a global minimum clock network augmentation algorithm, which inserts links simultaneously between all nearest sink pairs, apply rule-based link removal, and perform link consolidation by Steiner minimum tree construction for wirelength reduction with guaranteed clock skew yield. Our experimental results show that our proposed algorithm achieves dominant clock network augmentation solutions, e.g., an average of 16% clock skew yield improvement, 9% maximum skew reduction, and 25% reduction of clock skew variation standard deviation with identical wirelength compared with previous best clock network link insertion methods.|