|Title||Control-Flow Aware Communication and Conflict Analysis of Parallel Processes|
|Author||Axel Siebenborn, *Alexander Viehl, Oliver Bringmann (FZI Forschungszentrum Informatik, Germany), Wolfgang Rosenstiel (Universität Tübingen, Germany)|
|Page||pp. 32 - 37|
|Keyword||Architectural Exploration, Performance Analysis, Environment Modeling, Bus Allocation, SystemC|
|Abstract||In this paper, we present an approach for control-flow aware communication and conflict analysis of systems of parallel communicating processes. This approach allows to determine the global timing behavior of such a system and to detect communication that might produce conflicts on shared communication resources.
Furthermore, we show the incorporation of temporal environment models in order to analyze their influence on the system behavior. Based on the determined conflicts, an automated allocation and binding approach for shared resources to resolve potential access conflicts is proposed. All analysis steps can be performed starting with a TLM SystemC model of the entire system without any need for user interaction.
Finally, a SystemC model of a Viterbi decoder is used as case study to demonstrate the capability of our approach.|
|Title||Software Performance Estimation in MPSoC Design|
|Author||Marcio Oyamada, *Flavio Wagner (UFRGS, Brazil), Marius Bonaciu (TIMA Lab., France), Wander Cesario (MnD, France), Ahmed Jerraya (TIMA Lab., France)|
|Page||pp. 38 - 43|
|Keyword||Performance Estimation, MPSoC|
|Abstract||Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-dominated embedded systems. This work proposes an integrated methodology for system design and performance analysis. An analytic approach based on neural networks is used for high-level software performance estimation. At a functional level, this analytic tool enables a fast evaluation of the performance to be obtained with selected processors, which is an essential task for the definition of a “golden” architecture. From this architectural definition, a tool that refines hardware and software interfaces produces a bus-functional model. A virtual prototype is then generated from the bus-functional model, providing a global, cycle-accurate simulation model and offering several features for design validation and detailed performance analysis. Our work thus combines an analytic approach at functional level and a simulation-based approach at bus functional level. This provides an adequate trade-off between estimation time and precision. A multiprocessor platform implementing an MPEG4 encoder is used as case study, and the analytic estimation results in errors only up to 17% compared to the virtual platform simulation. On the other hand, the analytic estimation time takes only 17 seconds, against 10 minutes using the cycle-accurate simulation model.|
|Title||Effective OpenMP Implementation and Translation for Multiprocessor System-On-Chip without using OS|
|Author||*Woo-Chul Jeun, Soonhoi Ha (Seoul National University, Republic of Korea)|
|Page||pp. 44 - 49|
|Keyword||OpenMP, MPSoC, parallel programming, shared memory, synchronization|
|Abstract||It is attractive to use the OpenMP as a parallel programming model on a Multiprocessor System-On-Chip (MPSoC) because it is easy to write a parallel program in the OpenMP and there is no standard method for parallel programming on an MPSoC. In this paper, we propose an effective OpenMP implementation and translation for major OpenMP directives on an MPSoC with physically shared memories, hardware semaphores, and no operating system.|
|Title||Creating Explicit Communication in SoC Models Using Interactive Re-Coding|
|Author||*Pramod Chandraiah, Junyu Peng, Rainer Doemer (University of California, Irvine, United States)|
|Page||pp. 50 - 55|
|Keyword||System Level Design, SoC Specification, Refinement, Modeling, Design Methodology|
|Abstract||Communication exploration has become a critical step during SoC design.
Researchers in the CAD community have proposed
fast and efficient techniques
for comprehensive design space exploration to expedite this critical
Although these advances have been helpful in reducing the design time
significantly, the overall design time of the system is still
a bottleneck. All these techniques
assume the availability of an initial SoC input model with explicit communication,whose quality significantly impacts the effectiveness of the communication exploration techniques. Today, these initial models need to be manually written by engineers, which is tedious, error-prone and time consuming.In fact, our studies on industrial-size examples have shown that about 50% of the communication exploration time is spent on coding and re-coding of the initial specification model.
In this paper,we propose an efficient interactive approach to explicit communication creation by automating some of the common coding tasks
in specification models for communication exploration. Our results
show significant savings in designer time.|