|Title||LEAF: A System Level Leakage-Aware Floorplanner for SoCs|
|Author||*Aseem Gupta, Nikil Dutt, Fadi Kurdahi (University of California, Irvine, United States), Kamal Khouri, Magdy Abadir (Freescale Semiconductor Inc., United States)|
|Page||pp. 274 - 279|
|Keyword||Leakage Power, Floorplanner, Temperature, System Level|
|Abstract||Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). Hence, in this paper we propose a novel system level Leakage Aware Floorplanner (LEAF) which optimizes floorplans for temperature-aware leakage power along with the traditional metrics of area and wire length. Our floorplanner takes a SoC netlist and the dynamic power profile of functional blocks to determine a placement while optimizing for temperature dependent leakage power, area, and wire length. To demonstrate the effectiveness of LEAF, we implemented our methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and evaluated the trade-off between leakage power and area. We observed up to 190% difference in leakage power between leakage-unaware and leakage aware floorplanning.|
|Title||Protocol Transducer Synthesis using Divide and Conquer Approach|
|Author||*Shota Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita (University of Tokyo, Japan)|
|Page||pp. 280 - 285|
|Keyword||protocol, transducer, interface, NoC, wrapper|
|Abstract||In IP based design, the designers try to reuse existing IPs as much as possible.
Since currently available IPs use various communication protocols, protocol conversion is one of the most important topics in IP-based design.
We propose a method for automatic protocol transducer synthesis which is applicable to complex protocols.
The main idea of our proposed method is protocol transducer synthesis with a divide and conquer approach.
We demonstrate our method by synthesizing transducers which translate among the real and complicated protocols with advanced features such as non-blocking transactions and out-of-order transactions.|
|Title||A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units|
|Author||*Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Graduate School of Information Science and Technology, Osaka University, Japan)|
|Page||pp. 286 - 291|
|Keyword||ASIP (Application Specific Instruction-set Processor), Design Space Exploration, Architectural Description Language (ADL), Behavior Description, Micro Operation Description|
|Abstract||This paper proposes a method of generating a pipeline processor from behavior description.
In the proposed method, micro operation description is generated by complementing the behavior description
with specification of pipeline stages and functional units.
From the micro operation description, synthesizable HDL description of a processor can be generated.
The proposed method makes it possible to
reduce code size of architectural description language and
design time drastically without degradation of design quality, compared with the conventional method.|
|Title||Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture|
|Author||*Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe University, Japan)|
|Page||pp. 292 - 297|
|Keyword||H.264, Decoder, Low power, Elastic pipeline, Dynamic Voltage Scaling|
|Abstract||We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. The proposed pipeline can also reduce required local bus bandwidth. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The proposed architecture reduces power to 56% in a 90-nm process technology, compared to the conventional clock-gating scheme or local bus bandwidth to 37.2%.|
|Title||Architectural Optimizations for Text to Speech Synthesis in Embedded Systems|
|Author||*Soumyajit Dey, Monu Kedia, Anupam Basu (Indian Institute of Technology Kharagpur, India)|
|Page||pp. 298 - 303|
|Keyword||Text to Speech Synthesis (TTS), Natural Language Processing (NLP), Instruction Set Simulation (ISS), Throughput, Co-simulation|
|Abstract||The increasing processing power of embedded devices have created the scope for certain applications that could previously be executed in desktop environments only, to migrate into handheld platforms. An important feature of the computing systems of modern times is their support for applications that interact with the user by synthesizing natural speech output. Such applications deliver state of the art performance in desktop environments. However, the real-time performance of such applications in handheld platforms with on-line incoming text streams have not been explored till date. In this work, the performance of a Text to Speech Synthesis application is evaluated on embedded processor architectures and modiﬁcations in the underlying hardware platform are proposed for realtime performance improvement of the concerned application.|