| Title | (Invited Paper) Model-based Programming Environment of Embedded Software for MPSoC |
| Author | *Soonhoi Ha (Seoul National Univ., Republic of Korea) |
| Page | pp. 330 - 335 |
| Keyword | Embedded software, MPSoC, model-based design, common intermediate code |
| Abstract | A noble model-based programming environment of embedded software for MPSoC is proposed. By defining a common intermediate code (CIC), it separates modeling of the software and implementation optimized for target architecture. It also allows us to use diverse models for initial specification. Another feature is to provide multi-phase debugging capabilities: at the modeling stage, at the code generation stage, and at the simulation stage. Preliminary experiments with a Divx player confirm the feasibility and validity of the proposed technique. |
| Title | (Invited Paper) Energy-efficient Real-time Task Scheduling in Multiprocessor DVS Systems |
| Author | *Jian-Jia Chen, Chuan-Yue Yang, Tei-Wei Kuo, Chi-Sheng Shih (National Taiwan Univ., Taiwan) |
| Page | pp. 342 - 349 |
| Keyword | Energy-Efficient Scheduling, Real-Time Systems , DVS, Multiprocessor Systems |
| Abstract | Dynamic voltage scaling (DVS) circuits have been widely adopted in
many computing systems to provide tradeoff between performance and
power consumption. The effective use of energy could not only extend
operation duration for hand-held devices but also cut down power
bills of server systems. Moreover, while many chip makers are
releasing multi-core chips and multiprocessor system-on-a-chips
(SoCs), multiprocessor platforms for different applications become
even more popular. Multiprocessor platforms could improve the
system performance and accommodate the growing demand of computing
power and the variety of application functionality. This paper
summarizes our work on several important issues in energy-efficient
scheduling for real-time tasks in multiprocessor DVS systems.
Distinct from most previous work based on heuristics, we aim at the
provision of approximated solutions with worst-case guarantees. The
proposed algorithms are evaluated by a series of experiments to
provide insights in system designs. |