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The 12th Asia and South Pacific Design Automation Conference

Session 4D SPECIAL SESSION: EDA Challenges for Analog/RF
Time: 10:15 - 12:20 Thursday, January 25, 2007
Location: Room 416+417
Chair: Georges Gielen (Katholieke Universiteit Leuven, Belgium)

4D-1 (Time: 10:15 - 10:40)
Title(Invited Paper) Design Tool Solutions for Mixed-signal/RF Circuit Design in CMOS Nanometer Technologies
Author*Georges Gielen (Katholieke Universiteit Leuven, Belgium)
Pagepp. 432 - 437
Keywordanalog, mixed-signal, CAD tools
AbstractThe scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into the nanometer era also brings problems of leakage power, increasing variability and degradation, reducing supply voltages and worsening signal integrity conditions, all this in combination with tightening time-to-market constraints. Design methodologies and tools need to be developed to address these problems. This invited paper describes progress in modeling techniques for design and verification of complex integrated systems, in circuit and yield optimization tools for analog/RF circuits, as well as in signal integrity analysis methods such as EMC/EMI analysis.

4D-2 (Time: 10:40 - 11:05)
Title(Invited Paper) Challenges to Accuracy for the Design of Deep-submicron RF-CMOS Circuits
Author*Sadayuki Yoshitomi (Toshiba Corporation, Japan)
Pagepp. 438 - 441
KeywordRF-CMOS, Electro-Magnetic simulation, EKV3.0 , Compact Model, NQS effect
AbstractIncreasing complexity, functionality and operating frequency makes RF-CMOS circuit design a tough subject. Efficient use of recent electro-magnetic simulation, which enables the inclusion of many high-frequency effects, and the usage of "more" accurate compact models are the key to overcome this problem. Challenges of these two issues will be shown by the use of real implementation examples.

4D-3 (Time: 11:05 - 11:30)
Title(Invited Paper) Advanced Tools for Simulation and Design of Oscillators/PLLs
AuthorXiaolue Lai, *Jaijeet Roychowdhury (Univ. of Minnesota, United States)
Pagepp. 442 - 449
Keywordmacromodeling
AbstractThe lack of fast yet accurate oscillator and PLL simulation methods has constituted a serious bottleneck in mixed-signal, RF and digital design flows. Methods are described that, given differential equations for any oscillator (ie, equivalent to, eg, a SPICE-level circuit), will extract a simple nonlinear phase macromodel. It will be shown how such nonlinear phase macromodels are capable of capturing a variety of important effects, including jitter and phase noise, injection locking, PLL lock and capture phenomena, cycle slipping, etc., while being faster by several orders of magnitude than SPICE-level simulations. It will also be shown how this nonlinear phase macromodel, when applied to large systems of networked biochemical and and nanoelectronic oscillators, correctly predicts spontaneous pattern formation and edge detection.