The 12th Asia and South Pacific Design Automation Conference Technical Program

The 12th Asia and South Pacific Design Automation Conference

Session 6D Designers' Forum: Low-power SoC Technologies
Time: 16:00 - 17:50 Thursday, January 25, 2007
Location: Small Auditorium, 5F
Chairs: Haruyuki Tago (Toshiba Corporation, Japan), Kazutoshi Kobayashi (Kyoto University, Japan)

6D-1 (Time: 16:00 - 16:20)

Title	(Invited Paper) Plenary Talk --Overview on Low Power SoC Design Technology--
Author	*Kimiyoshi Usami (Shibaura Institute of Technology, Japan)
Page	pp. 634 - 636
Keyword	low power, leakage, power gating
Abstract	So far, low power design for SoC has mainly focused on techniques to reduce dynamic power and standby leakage power. In further scaled devices, design technology to reduce active leakage power at the operation mode becomes indispensable. This is because the share of leakage power in the total operation power continues to increase as the device gets scaled. This paper gives a brief overview on the conventional leakage reduction techniques and describes novel approaches to use run-time power gating for active leakage reduction.

6D-2 (Time: 16:20 - 16:50)

Title	(Invited Paper) Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware
Author	*Masaru Hase, Kazushi Akie, Masaki Nobori, Keisuke Matsumoto (Renesas Technology, Japan)
Page	pp. 637 - 643
Keyword	Codec, VC-1, H.264, MPEG-4, IP
Abstract	This paper covers a multi-functional hardware intellectual property (IP) for the encoding and decoding of digital moving pictures with low power consumption. The IP is mainly intended for mobile products such as cellular phones, digital still cameras (DSCs), and digital video cameras (DVCs). It includes VC-1 functionality for Internet content plus AVC (H.264) functionality for digital television broadcasting and MPEG-4 functionality for TV telephony, and is capable of processing D1-sized moving pictures (720 pixels by 480 lines) in real time at an operating frequency of 54 MHz. In addition, original algorithms employed in the IP reduce power consumption by up to 22%.

6D-3 (Time: 16:50 - 17:20)

Title	(Invited Paper) Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G)
Author	*Koichi Mori, Masakazu Suzuki, Yasuo Ohara, Satoru Matsuo, Atsushi Asano (Toshiba, Japan)
Page	pp. 644 - 648
Keyword	ISDB-T, Low Power, Multi-Media, Processor, Mobile Communication
Abstract	TOSHIBA has developed mobile multi-media engine SoC, we call as S1G, which can realize low power ISDB-T one-segment decode in 42mW for eight months short period of time. Since MPEG2 TS de-multiplexing, AAC decoding and H.264 decoding should be simultaneously processed in ISDB-T one-segment decode, two TOSHIBA MeP (Media embedded Processor) processors and one DSP and hardware blocks are used effectively with pipeline operation in this LSI. Although it is generally considered that dedicated hardware accelerator should be used to realize low power operation for ISDB-T one-segment decode, TOSHBA succeeded in developing low power ISDB-T one-segment decoder using maximum software resources.

6D-4 (Time: 17:20 - 17:50)

Title	(Invited Paper) Low Power Techniques for Mobile Application SoCs based on Integrated Platform "UniPhier"
Author	*Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita (Matsushita Electric Industrial, Japan)
Page	pp. 649 - 653
Keyword	Low Power
Abstract	On this presentation, Low Power Techniques for Mobile application SoCs based on Integrated Platform "UniPhier" are introduced. For SoCs, Hierarchical power reduction approaches of each Soc architecture level, UniPhier Processor level, IPP Processor level, and Circuit level are prepared. In case of development of UniPhier base SoC for mobile application, we can pick the combination of suitable low power techniques to realize the target and can make a trade-off between power and cost.