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## The 12th Asia and South Pacific Design Automation Conference

Session 7B Uncertainty Aware Interconnect Design
Time: 10:15 - 12:20 Friday, January 26, 2007
Location: Room 413
Chairs: Chih-Tsun Huang (National Tsing Hua Univ., Taiwan), Takashi Sato (Tokyo Inst. of Tech., Japan)

7B-1 (Time: 10:15 - 10:40)
 Title Approaching Speed-of-light Distortionless Communication for On-chip Interconnect Author Haikun Zhu, Rui Shi (University of California, San Diego, United States), Hongyu Chen (Synopsys Inc., United States), *Chung-Kuan Cheng (University of California, San Diego, United States) Page pp. 684 - 689 Keyword global interconnect, transmission line, distortionless, speed-of-light, serial link Abstract We extend the Surfliner on-chip distortionless transmission line scheme and provide more details for the implementation issues. Surfliner seeks to approach distortionless transmission by intentionally adding shunt resistors between the signal line and the ground. In theory if we distributively make the shunt conductance G=RC/L, there will be no distortion at the receiver end and the signal propagates at the speed of light. We show the feasibility and advantages of this shunt resistor scheme by a real design case of single-ended microstrip line in 0.10$\mu$m technology. The simulation results indicate we can achieve near perfect signaling of 10 Gbps data over a 10 mm serial link, yet no pre-emphasis/equalization or other special techniques are needed. Guidelines for determining the optimal value and spacing of the shunt resistors are also provided.

7B-2 (Time: 10:40 - 11:05)
 Title Delay Uncertainty Reduction by Interconnect and Gate Splitting Author Vineet Agarwal, Jin Sun, Alexandar Mitev, *Janet Wang (University of Arizona at Tucson, United States) Page pp. 690 - 695 Keyword gate splitting, interconnect splitting Abstract Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective splitting based variation reduction techniques for both interconnects and gates. We developed a new tool called Timing Uncertainty Reduction by Gate-Interconnect Splitting which reduces the timing variations of a circuit. It is shown that using splitting on interconnect can reduce the Chemical-Mechanical Polishing (CMP) induced dishing effect and can result in decrease at an average of 5% in mean interconnect delay in addition to decrease in its variation. Improvements of up to 30\% are achieved on timing variation for gates of various size while reduction of 55% can be observed in interconnect delay variation.

7B-3 (Time: 11:05 - 11:30)
 Title Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects Author *Charbel Akl, Magdy Bayoumi (University of Louisiana at Lafayette, United States) Page pp. 696 - 701 Keyword encoding, repeaters Abstract Global signaling is becoming more and more challenging as technology scales down toward the deep submicron. We propose a new bus encoding technique, transition skew coding, that targets many of the global interconnects challenges such as crosstalk, peak energy and current, switching and leakage power, repeaters area, wiring area, signal integrity and noise. Simulations are done on different bus lengths using a 90 nm library. Repeaters sizing and spacing are optimized, and the proposed encoded bus is compared against a standard bus and a bus with shields inserted between every two wires. The encoding and decoding latencies are also analyzed. Simulations show that transition skew coding is efficient in terms of energy and area with low encoding and decoding latency overhead.

7B-4 (Time: 11:30 - 11:55)
 Title Fast Buffered Delay Estimation Considering Process Variations Author Tien-Ting Fang, *Ting-Chi Wang (National Tsing Hua University, Taiwan) Page pp. 702 - 707 Keyword buffer, timing estimation, statistical, process variations Abstract Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations becomes critical to ensure high parametric timing yield. During the design stage, fast estimation of the achievable buffered delay can navigate more accurate and efficient wire planning and timing analysis in floorplanning or global routing. In this paper, we derive approximated first-order canonical forms for buffered delay estimation which considers the effect of process variations and the presence of buffer blockages. We empirically show that an existing deterministic delay estimation method will be over-pessimistic and thus result in unnecessary design rollback. The experimental results also show that our method can estimate buffered delay with 4% average error but achieve up to 149 times speedup when compared to a state-of-the-art statistical buffer insertion method.

7B-5 (Time: 11:55 - 12:20)
 Title Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect Author *Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud (Rice University, United States) Page pp. 708 - 713 Keyword carbon nanotube, modeling, alternative interconnect technologies Abstract Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnect. In this paper, we evaluate the performance and reliability of nanotube bundles for future VLSI applications. We develop a scalable equivalent circuit model that captures the statistical distribution of metallic nanotubes while accurately incorporating recent experimental and theoretical results on inductance, contact resistance, and ohmic resistance. Leveraging the circuit model, we examine the performance and reliability of nanotube bundles including inductive effects. The results indicate that SWCNT interconnect bundles can provide significant improvement in delay over copper interconnect depending on the bundle geometry and process technology.