|Title||A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture|
|Author||*Seongmoon Wang, Wenlong Wei (NEC Labs., America, United States)|
|Page||pp. 810 - 816|
|Keyword||low power testing, scan based testing, power dissipation during test application, low switching activity|
|Abstract||In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The peak transition is reduced by about 40% and average number of transitions is reduced by about 56-75%.
This reduction in peak and average switching is achieved without any decrease in fault coverage.
The proposed method does not require any specific clock tree
construction, special scan cells, or scan chain routing.
Test cubes generated by any combinational ATPG can be processed by the proposed method to reduce peak and average switching activity without any capture violation.
Hardware overhead for the proposed method is negligible.
Further, the hardware for the proposed method can be implemented without detailed knowledge of the design.|
|Title||Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes|
|Author||Zhuo Zhang, *Sudhakar Reddy (University of Iowa, United States), Irith Pomeranz (Purdue University, United States)|
|Page||pp. 817 - 822|
|Keyword||transition delay fault, launch off shift, test escape, functionally detectable faults|
|Abstract||A concern expressed often in the literature is the potential over testing or yield loss caused by the fact that launch off shift operates the circuit under test in non-functional manner. In this paper we present data, for the first time, which points to another potential problem with launch off shift tests - test escapes. We also present data that shows that if launch off shift tests with multiple fault activation cycles are used essentially all functionally detectable faults can be detected.|
|Title||A Wafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs|
|Author||Sudarshan Bahukudumbi, Sule Ozev, *Krishnendu Chakrabarty (Duke University, United States), Vikram Iyengar (IBM Corporation, United States)|
|Page||pp. 823 - 828|
|Keyword||SoC test, cost model, wafer-level defect screening|
|Abstract||Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of "big-D/small-A" mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss and packaging costs. Experimental results are presented for a typical mixed-signal "big-D/small-A" SoC, which contains a large section of flattened digital logic and several large mixed-signal cores. |
|Title||Fault Dictionary Size Reduction for Million-Gate Large Circuits|
|Author||*Yu-Ru Hong, Juinn-Dar Huang (National Chiao Tung University, Taiwan)|
|Page||pp. 829 - 834|
|Keyword||fault diagnosis, fault dictionary, fault dictionary size reduction, pass-fail fault dictionary|
|Abstract||In general, fault dictionary is prevented from practical applications for its extremely large size. Several previous works are proposed for the fault dictionary size reduction. However, they might not be able to handle today’s million-gate circuits due to the high time and space complexity. In this paper, we propose an algorithm to significantly reduce the size of fault dictionary while still preserving high diagnostic resolution. The proposed algorithm possesses extremely low time and space complexity by avoiding constructing the huge distinguishability table, which inevitably boosts up the required computation complexity. Experimental results demonstrate that the proposed algorithm is fully capable of handling industrial million-gate large circuits in a reasonable amount of runtime and memory.|
|Title||Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies|
|Author||*Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li (Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan)|
|Page||pp. 835 - 840|
|Keyword||Fault Diagnosis, BIST, CPRS, Scan Chain, Unknowns|
|Abstract||A Cyclic-CPRS (Column Parity Row Selection) technique is presented to diagnose built-in self tested (BISTed) circuits, even in the presence of many unknowns and transient errors. The novel cyclic scan chains retain the transient errors and unknowns in the CUT until they are fully diagnosed. Instead of masking the unknowns, Cyclic-CPRS directly diagnoses the unknowns as if they were errors. Direct diagnosis of unknowns not only eliminates the masking circuitry but also enhances the diagnosis resolution. Experimental results show that Cyclic-CPRS is very successful even in the presence of 10% errors and unknowns. The proposed technique is especially suitable for nano-meter technologies, in which transient errors and systematic defects are becoming serious problems.|