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The 12th Asia and South Pacific Design Automation Conference

Session 9A Power Efficient Design Techniques
Time: 16:00 - 18:05 Friday, January 26, 2007
Location: Room 411+412
Chairs: Hiroyuki Tomiyama (Nagoya Univ., Japan), Gang Zeng (Nagoya Univ., Japan)

9A-1 (Time: 16:00 - 16:25)
TitleFlow Time Minimization under Energy Constraints
Author*Jian-Jia Chen (National Taiwan Univ., Taiwan), Kazuo Iwama (Kyoto Univ., Japan), Tei-Wei Kuo, Hseuh-I Lu (National Taiwan Univ., Taiwan)
Pagepp. 866 - 871
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9A-2 (Time: 16:25 - 16:50)
TitleIntegrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost
AuthorBita Gorjiara, Nader Bagherzadeh, *Pai Chou (Univ. of California, Irvine, United States)
Pagepp. 872 - 877
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9A-3 (Time: 16:50 - 17:15)
TitleA Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
Author*Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ., Japan)
Pagepp. 878 - 883
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9A-4 (Time: 17:15 - 17:40)
TitleProgram Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency
Author*Subhasis Banerjee (Sun Microsystems, India), Surendra G, S. K. Nandy (Indian Institute of Science, India)
Pagepp. 884 - 889
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9A-5 (Time: 17:40 - 18:05)
TitleCLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time
Author*Jorgen Peddersen, Sri Parameswaran (Univ. of New South Wales, Australia)
Pagepp. 890 - 895
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