Session 5C: Thermal Analysis and DFM

5C-1 (Time: 13:30 - 13:55)

Title Architecture-level Thermal Behavioral Characterization For Multi-Core Microprocessors
Author Duo Li, *Sheldon X.-D. Tan (Univ. of California, Riverside, USA), Murli Tirumala (Intel, USA)
Abstract In this paper, we investigate a new architecture-level thermal characterization problem from behavioral modeling perspective to address the emerging thermal related analysis and optimization problems for high-performance multi-core microprocessor design. We propose a new approach, called ThermPOF, to build the thermal behavioral models from the measured architecture thermal and power information. ThermPOF first builds the behavioral thermal model using generalized pencil-of-function (GPOF) method. And then to effectively model transient temperature changes, we proposed two new schemes to improve the GPOF. First we apply logarithmic-scale sampling instead of traditional linear sampling to better capture the temperature changing characteristics. Second, we modify the extracted thermal impulse response such that the extracted poles from GPOF are guaranteed to be stable without accuracy loss. To further reduce the model size, Krylov subspace based model order reduction is performed to reduce the order of the models in the state-space form. Experimental results on a practical quad-core microprocessor show that generated thermal behavioral models match the measured data very well.

5C-2 (Time: 13:55 - 14:20)

Title Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms
Author *Pei-Yu Huang, Chih-Kang Lin, Yu-Min Lee (Nat’l Chiao Tung Univ., Taiwan)
Abstract The capability of predicting the temperature profile is critically important for circuit timing estimation, leakage reduction, power estimation, hotspot avoidance, and reliability concerns during modern IC designs. This paper presents an accurate and fast analytical full-chip thermal simulator for the early-stage temperature-aware chip design. By using the technique of generalized integral transforms (GIT), our proposed method can accurately estimate the temperature distribution of full-chip with very small truncation points of bases in the spatial domain. We also develop a fast Fourier transform (FFT) like evaluating algorithm to efficiently evaluate the temperature distribution. Experimental results confirm that our GIT based analyzer can achieve an order of magnitude speedup compared with a highly efficient Green's function based method.
No Slides

5C-3 (Time: 14:20 - 14:45)

Title A Stochastic Local Hot Spot Alerting Technique
Author Hwisung Jung, *Massoud Pedram (Univ. of Southern California, USA)
Abstract With the increasing levels of variability in the behavior of manufactured nano-scale devices and dramatic changes in the power density on a chip, timely identification of hot spots on a chip has become a challenging task. This paper addresses the questions of how and when to identify and issue a hot spot alert. There are important questions since temperature reports by thermal sensors may be erroneous, noisy, or arrive too late to enable effective application of thermal management mechanisms to avoid chip failure. This paper thus presents a stochastic technique for identifying and reporting local hot spots under probabilistic conditions induced by uncertainty in the chip junction temperature and the system power state. More specifically, it introduces a stochastic framework for estimating the chip temperature and the power state of the system based on a combination of Kalman Filtering (KF) and Markovian Decision Process (MDP) model. Experimental results demonstrate the effectiveness of the framework and show that the proposed technique alerts about thermal threats accurately and in a timely fashion in spite of noisy or sometimes erroneous readings by the temperature sensor.

5C-4 (Time: 14:45 - 15:10)

Title Design Rule Optimization of Regular layout for Leakage Reduction in Nanoscale Design
Author Anupama R. Subramaniam (Arizona State Univ., USA), Ritu Singhal, *Chi-Chao Wang, Yu Cao (Arizona State Univ., USA)
Abstract The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic procedure to optimize key layout parameters in regular layout with minimum area and speed overhead. As demonstrated in 65nm technology, the optimization of regular layout achieves more than 70% reduction in leakage under NRG, with area penalty of ~10% and marginal impact on circuit speed and active power.

5C-5 (Time: 15:10 - 15:35)

Title Investigation of Diffusion Rounding for Post-Lithography Analysis
Author Puneet Gupta (Univ. of California, Los Angles, USA), Andrew B. Kahng (Univ. of California, San Diego, USA), *Youngmin Kim (Univ. of Michigan, Ann Arbor, USA), Saumil Shah (Blaze-DFM, USA), Dennis Sylvester (Univ. of Michigan, Ann Arbor, USA)
Abstract Due to aggressive scaling of device feature size to improve circuit performance in the sub-wavelength lithography regime, both diffusion and poly gate shapes are no longer rectilinear. Diffusion rounding occurs most notably where the diffusion shapes are not perfectly rectangular, including common L and T-shaped diffusion layouts to connect to power rails. This paper investigates the impact of the non-rectilinear shape of diffusion (i.e., sloped diffusion or diffusion rounding) on circuit performance (delay and leakage). Simple weighting function models for Ion and Ioff to account for the diffusion rounding effects are proposed, and compared with TCAD simulation. Our experiments show that diffusion rounding has an asymmetric characteristic for Ioff due to the differing significance of source/drain junctions on device threshold voltage. Therefore, we can model Ion and Ioff as a function of slope angle and direction. The proposed models match well with TCAD simulation results, with less than 2% and 6% error in Ion and Ioff, respectively.
Last Updated on: January 31, 2008