| Title | Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning |
| Author | Feng Wang, *Xiaoxia Wu, Yuan Xie (Pennsylvania State Univ., United States) |
| Page | pp. 2 - 9 |
| Detailed information (abstract, keywords, etc) | |
| Title | Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA |
| Author | *Cheng-Tao Hsieh (Nat'l Tsing Hua Univ., Taiwan), Jason Cong, Zhiru Zhang (Univ. of California, Los Angeles, United States), Shih-Chieh Chang (Nat'l Tsing Hua Univ., Taiwan) |
| Page | pp. 10 - 15 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Multicycle Communication Architecture and Synthesis Flow for Global Interconnect Resource Sharing |
| Author | Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, *Ya-Shih Huang (Nat'l Chiao Tung Univ., Taiwan) |
| Page | pp. 16 - 21 |
| Detailed information (abstract, keywords, etc) | |
| Title | Scheduling with Integer Time Budgeting for Low-Power Optimization |
| Author | Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, *Jason Cong (Univ. of California, Los Angeles, United States) |
| Page | pp. 22 - 27 |
| Detailed information (abstract, keywords, etc) | |
| Title | REWIRED - Register Write Inhibition by Resource Dedication |
| Author | *Pushkar Tripathi, Rohan Jain (Indian Inst. of Tech. Delhi, India), Srikanth Kurra (Oracle, India), Preeti Ranjan Panda (Indian Inst. of Tech. Delhi, India) |
| Page | pp. 28 - 31 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Efficient Performance Improvement Method Utilizing Specialized Functional Units in Behavioral Synthesis |
| Author | *Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ., Japan) |
| Page | pp. 32 - 35 |
| Detailed information (abstract, keywords, etc) | |