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The 13th Asia and South Pacific Design Automation Conference

Session 5A  Techniques for Formal and Simulation-Based Varification
Time: 13:30 - 15:35 Wednesday, January 23, 2008
Location: Room 310A
Chairs: Sherief Reda (Brown Univ., United States), Jin-Young Choi (Korea Univ., Republic of Korea)

5A-1 (Time: 13:30 - 13:55)
TitleVerifying Full-Custom Multipliers by Boolean Equivalence Checking and an Arithmetic Bit Level Proof
Author*Udo Krautz, Markus Wedler, Wolfgang Kunz (Univ. Kaiserslautern, Germany), Kai Weber, Christian Jacobi, Matthias Pflanz (IBM, Germany)
Pagepp. 398 - 403
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5A-2 (Time: 13:55 - 14:20)
TitleA Symbolic Approach for Mixed-Signal Model Checking
Author*Alexander Jesser, Lars Hedrich (Univ. of Frankfurt a.M., Germany)
Pagepp. 404 - 409
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5A-3 (Time: 14:20 - 14:45)
TitleFaster Projection Based Methods for Circuit Level Verification
Author*Chao Yan, Mark Greenstreet (Univ. of British Columbia, Canada)
Pagepp. 410 - 415
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5A-4 (Time: 14:45 - 15:10)
TitleA Debug Probe for Concurrently Debugging Multiple Embedded Cores and Inter-Core Transactions in NoC-Based Systems
AuthorShan Tang, *Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 416 - 421
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5A-5 (Time: 15:10 - 15:23)
TitleA Fast Two-Pass HDL Simulation with On-Demand Dump
Author*Kyuho Shim (Pusan Nat'l Univ., Republic of Korea), Youngrae Cho, Namdo Kim (Samsung Electronics, Republic of Korea), Hyuncheol Baik, Kyungkuk Kim, Dusung Kim (Pusan Nat'l Univ., Republic of Korea), Jaebum Kim, Byeongun Min, Kyumyung Choi (Samsung Electronics, Republic of Korea), Maciej Ciesielski (Logic-Mill Technology LLC, United States), Seiyang Yang (Pusan Nat'l Univ., Republic of Korea)
Pagepp. 422 - 427
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