| Title | Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering |
| Author | *Debasish Das (Northwestern Univ., United States), Kip Killpack, Chandramouli Kashyap, Abhijit Jas (Intel, United States), Hai Zhou (Northwestern Univ., United States) |
| Page | pp. 486 - 491 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Fast Incremental Clock Skew Scheduling Algorithm for Slack Optimization |
| Author | *Kui Wang, Hao Fang, Hu Xu, Xu Cheng (Peking Univ., China) |
| Page | pp. 492 - 497 |
| Detailed information (abstract, keywords, etc) | |
| Title | Clock Tree Synthesis with Data-Path Sensitivity Matching |
| Author | *Matthew R. Guthaus (Univ. of California Santa Cruz, United States), Dennis Sylvester (Univ. of Michigan, United States), Richard B. Brown (Univ. of Utah, United States) |
| Page | pp. 498 - 503 |
| Detailed information (abstract, keywords, etc) | |
| Title | Buffered Clock Tree Synthesis for 3D ICs Under Thermal Variations |
| Author | Jacob Minz (Synopsys, United States), Xin Zhao, *Sung Kyu Lim (Georgia Inst. of Tech., United States) |
| Page | pp. 504 - 509 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Delay Model for Interconnect Trees Based on ABCD Matrix |
| Author | *Guofei Zhou, Li Su, Depeng Jin, Lieguang Zeng (Tsinghua Univ., China) |
| Page | pp. 510 - 513 |
| Detailed information (abstract, keywords, etc) | |
| Title | Analytical Model for the Impact of Multiple Input Switching Noise on Timing |
| Author | Rajeshwary Tayade (Univ. of Texas, Austin, United States), *Sani Nassif (IBM, United States), Jacob Abraham (Univ. of Texas, Austin, United States) |
| Page | pp. 514 - 517 |
| Detailed information (abstract, keywords, etc) | |