| Title | A Unified Methodology for Power Supply Noise Reduction in Modern Microarchitecture Design |
| Author | Michael Healy, Fayez Mohamood, Hsien-Hsin S. Lee, *Sung Kyu Lim (Georgia Institute of Technology, United States) |
| Page | pp. 611 - 616 |
| Keyword | power noise, dynamic control, floorplanning |
| Abstract | In this paper, we present a novel design methodology to combat the ever-aggravating high frequency power supply noise (di/dt) in modern microprocessors. Our methodology integrates microarchitectural profiling for noise-aware floorplanning, dynamic runtime noise control to prevent unsustainable noise emergencies, as well as decap allocation; all to produce a design for the average-case current consumption scenario. The dynamic controller contributes a microarchitectural technique to eliminate occurences of the worst-case noise scenario thus our method focuses on average-case noise behavior. |
| Title | Heuristic Power/Ground Network and Floorplan Co-Design Method |
| Author | *Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong (Tsinghua University, China) |
| Page | pp. 617 - 622 |
| Keyword | Floorplan, IR drop, P/G network optimization |
| Abstract | It's a trend to consider power supply integrity at early stage to improve the design quality. In this paper, we propose a novel algorithm to optimize floorplan together with P/G network. Compared with previous methods, our algorithm can search the floorplan space more efficiently and therefore lead to better results. Further, we also propose a smart heuristic method to build P/G mesh grid with optimized topology. Experimental results show our method can speedup the floorplanning process by about 10 times and reduce the routing area of P/G network while maintaining the floorplan quality and P/G integrity. |
| Title | Vertical Via Design Techniques for Multi-Layered P/G Networks |
| Author | *Shuai Li, Jin Shi, Yici Cai, Xianlong Hong (Tsinghua University, China) |
| Page | pp. 623 - 628 |
| Keyword | P/G , multi-layered, via |
| Abstract | In multi-layered power/ground (P/G) networks, to connect the whole network together, vertical vias are usually placed at intersections between metal wires of adjoining layers. In this paper, a deep study about the design of vertical vias is presented. First we present an efficient heuristic algorithm based on sensitivity analysis to optimize via allocation in early design stage. Compared with equal allocation, averagely our algorithm is capable of reducing worst voltage drop by 8.43% while using the same or even less number of vias. Also, adjoint network method is utilized and significantly improves the efficiency of our algorithm. Next, we demonstrate that by linking metal wires of nonadjacent layers, cross-layer vias are powerful in eliminating “hot” areas which suffer from large voltage drop on bottom layer. A similar heuristic algorithm is also developed for the addition of cross-layer vias. |
| Title | Statistical Mixed Vt Allocation of Body-Biased Circuits for Reduced Leakage Variation |
| Author | Jinseob Jeong, *Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea) |
| Page | pp. 629 - 634 |
| Keyword | Statistical, Mixed Vt, Body Biasing |
| Abstract | Leakage current is susceptible to variation of transistor parameters and environment such as temperature, which results in wide spread in leakage distribution. The spread can be reduced by employing body biasing: reverse body bias for too leaky dies and forward body bias for too slow dies. We investigate body biasing of mixed Vt circuits. It is shown that the conventional body biasing has limitation in reducing leakage variation of mixed Vt circuits. This is because low- and high-Vt devices do not track each other and their body biasing sensitivities are different. We present alternative body biasing scheme that targets compensating die-to-die variation of low Vt. Under this body biasing scheme, within-die profiles of lowand high-Vt, which we need for statistical allocation of mixed Vt, get wider thus become different from the original ones. We present an analytical procedure to derive new within-die profiles. Experiments with 45-nm predictive model show that the spread in leakage can be reduced to 4.5 on average as opposed to 9.4 from conventional body biasing on mixed Vt circuits. |
| Title | Exploring High-Speed Low-Power Hybrid Arithmetic Units at Scaled Supply and Adaptive Clock-Stretching |
| Author | Swaroop Ghosh, *Kaushik Roy (Purdue Univ., United States) |
| Page | pp. 635 - 640 |
| Keyword | Low Power, adder, high speed, hybrid, robust |
| Abstract | In this paper, we explore various arithmetic units for possible use in high speed, high yield ALU design at scaled supply voltage with variable latency operation. We demonstrate that careful modification of the existing arithmetic units indeed make them further suitable for supply voltage scaling with tolerable area overhead. Simulation results on different adder and multiplier topologies show 18-60% improvement in power with 2-8% increase in die-area at iso-yield. We also extend our studies to design low power and high yield multipliers. These optimized low power datapath units can be used to construct a low power and robust ALU. |