| Title | Optimal Allocation and Placement of Thermal Sensors for Reconfigurable Systems and Its Practical Extension |
| Author | *ByungHyun Lee, Taewhan Kim (Seoul National University, Republic of Korea) |
| Page | pp. 703 - 707 |
| Keyword | thermal sensor, allocation, placement, optimization |
| Abstract | A dynamic monitoring of thermal behavior of hardware resources using thermal sensors is very important to maintain the operation of systems safe and reliable. This work proposes an effective solution to the problem of thermal sensor allocation and placement for reconfigurable systems at the post-manufacturing stage. Specifically, we define the sensor allocation and placement problem (SAPP), and propose a solution which formulates SAPP into the unate-covering problem (UCP) and solves it optimally. We then provide an extended solution to handle a practical design issue where the hardware resources for the sensor implementation on specific array locations have already been used up by the application logic. Experimental results using MCNC benchmarks show that our proposed technique uses 19.7% less number of sensors to monitor hotspots on the average than that used by the bisection based approaches. |
| Title | Exploring Power Management in Multi-Core Systems |
| Author | Reinaldo Bergamaschi (IBM T.J. Watson Research Center, United States), Guoling Han (University of California, Los Angeles, United States), Alper Buyuktosunoglu (IBM T.J. Watson Research Center, United States), Hiren Patel (Virginia Tech, United States), Indira Nair, *Gero Dittmann, Geert Janssen (IBM T.J. Watson Research Center, United States), Nagu Dhanwada (IBM EDA Laboratory, United States), Zhigang Hu, Pradip Bose, John Darringer (IBM T.J. Watson Research Center, United States) |
| Page | pp. 708 - 713 |
| Keyword | dynamic voltage and frequency scaling (DVFS), power management, multi-core systems modeling, performance and power simulation |
| Abstract | Power dissipation has become a critical design metric in microprocessor-based system design. In a multi-core system, running multiple applications, power and performance can be dynamically traded off using an integrated power management (PM) unit. This PM unit monitors the performance and power of each core and dynamically adjusts the individual voltages and frequencies in order to maximize system performance under a given power budget (usually set by the operating system). This paper presents a performance and power analysis methodology, featuring a simulation model for multi-core systems that can be easily reconfigured for different scenarios and a PM infrastructure for the exploration and analysis of PM algorithms. Two algorithms have been implemented: one for discrete and one for continuous power modes based on non-linear programming. Extensive experiments are reported, illustrating the effect of power management both at the core and the chip level. |
| Title | Dependability, Power, and Performance Trade-Off on a Multicore Processor |
| Author | *Toshinori Sato (Kyushu University, Japan), Toshimasa Funaki (Kyushu Institute of Technology, Japan) |
| Page | pp. 714 - 719 |
| Keyword | power consumption, dependability, multicore processors, trade-off design, soft errors |
| Abstract | As deep submicron technologies are advanced, we face new challenges, such as power consumption and soft errors. A naïve technique, which utilizes emerging multicore processors and relies upon thread-level redundancy to detect soft errors, is power hungry. It consumes at least two times larger power than the conventional single-threaded processor does. This paper investigates a trade-off between dependability and power on a multicore processor, which is named multiple clustered core processor (MCCP). It is proposed to adapt processor resources according to the requested performance. A new metric to evaluate a trade-off between dependability, power, and performance is proposed. It is the product of soft error rate and the popular energy-delay product. We name it energy, delay, and upset rate product (EDUP). Detailed simulations show that the MCCP exploiting the adaptable technique improves the EDUP by up to 21% when it is compared with the one exploiting the naïve technique. |
| Title | High Performance Current-Mode Differential Logic |
| Author | Ling Zhang (Univ. of California, San Diego, United States), Jianhua Liu (Altera, United States), Haikun Zhu (Qualcomm, United States), *Chung-Kuan Cheng (Univ. of California, San Diego, United States), Masanori Hashimoto (Osaka Univ., Japan) |
| Page | pp. 720 - 725 |
| Keyword | VLSI circuit design, differential logic, current-mode logic |
| Abstract | This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage swing (LVS) logic, CMDL uses a shunt resistor at the differential output to obtain constant low swing signal without the need to reset low. Furthermore, conditional shunt transistors are used for the internal nodes to prevent high-voltage swing, thus entirely eliminate the power-hungry clocked reset network in LVS circuits. We show that the CMDL is suitable for high-end microprocessor integer core by providing three datapath modules implemented in CMDL. Our simulation results indicate that, operating at comparable speed with LVS logic, CMDL circuits can achieve up to 50% reduction of delay-power product compared to CMOS logic and LVS logic. In addition, CMDL reduces the power consumption of LVS by up to 40%. |
| Title | NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution? |
| Author | Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, *Kaushik Roy (Purdue Univ., United States) |
| Page | pp. 726 - 731 |
| Keyword | Reliability, NBTI, Temporal degradation |
| Abstract | This paper evaluates the severity of negative bias temperature instability (NBTI) degradation in two major circuit applications: random logic and memory array. For improved lifetime stability, we propose/select an efficient relia- bility-aware circuit design methodologies. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. As a result, simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memory shows much severe effect especially when combined with the impact of random process variation, NBTI can dramatically reduce the READ stability of memory cells. Hence, aggressive design techniques such as stand-by VDD scaling or adaptive body biasing (ABB) are required in memory application to minimize the impact of NBTI. |