Tuesday, January 22, 2008 |
A | B | C | D |
---|---|---|---|
Opening Ceremony 08:30 - 09:00 |
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Keynote Session I 09:00 - 10:00 |
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10:00 - 10:15 |
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New Challenges in High Level Synthesis 10:15 - 12:20 |
Power and Thermal Modeling and Optimization 10:15 - 12:20 |
Emerging Technologies 10:15 - 12:20 |
University LSI Design Contest 10:15 - 12:20 |
12:20 - 13:30 |
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Advanced Topic in Logic Synthesis 13:30 - 15:35 |
Interconnect Modeling and Simulation Techniques 13:30 - 15:35 |
Floorplanning 13:30 - 15:35 |
Special Session - Tackling Manufacturability/Variability for 32nm and Below 13:30 - 15:35 |
15:35 - 15:50 |
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Routing 15:50 - 17:55 |
Interconnect, NoCs, and MPSoCs 15:50 - 17:30 |
Special Session (Panel) The Tears and Joy of Sowing and Reaping Complex SoC's 15:50 - 17:55 |
Wednesday, January 23, 2008 |
A | B | C | D |
---|---|---|---|
Keynote Session II 9:00 - 10:00 |
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10:00 - 10:15 |
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Variability Issues in Timing 10:15 - 12:20 |
Memory and Processor Optimization 10:15 - 12:20 |
New Techniques for Physical Design Optimization 10:15 - 12:20 |
Designers' Forum - New Emerging Application Areas for Future SoC 10:15 - 12:20 |
12:20 - 13:30 |
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Techniques for Formal and Simulation-Based Varification 13:30 - 15:35 |
Power and Performance Optimization for Embedded Systems 13:30 - 15:35 |
Thermal Analysis and DFM 13:30 - 15:35 |
Designers' Forum (Panel) Are System Level EDA Tools/Methodologies Coming? 13:30 - 15:35 |
15:35 - 15:50 |
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Trends in Timing 15:50 - 17:55 |
Statistical Modeling and Yield Prediction 15:50 - 17:55 |
Special Session - How to Design Cool Chips for Hot Products 15:50 - 17:55 |
Thursday, January 24, 2008 |
A | B | C | D |
---|---|---|---|
Keynote Session III 9:00 - 10:00 |
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10:00 - 10:15 |
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Reliable/Testable Design Techniques 10:15 - 12:20 |
Communication and Interfaces 10:15 - 12:20 |
Power: Delivery and Reduction 10:15 - 12:20 |
Special Session (Panel) Concurrent SoC and SiP Designs 10:15 - 12:20 |
12:20 - 13:30 |
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Test Generation and Test Power 13:30 - 15:35 |
Design Space Exploration 13:30 - 15:35 |
Reliability and Power Management 13:30 - 15:35 |
Designers' Forum - Low Power Chips 13:30 - 15:35 |
15:35 - 15:50 |
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Analog/RF/Mixed Signal CAD 15:50 - 17:55 |
Architecture Exploration 15:50 - 17:55 |
Designers' Forum (Panel) Best Ways to Use Billions of Devices on a Chip 15:50 - 17:55 |
Tuesday, January 22, 2008 |
Title | (Keynote Address) A Brand New Wireless Day |
Author | *Jan M. Rabaey (Univ. of California, Berkeley, United States) |
Page | p. 1 |
Detailed information (abstract, keywords, etc) |
Title | Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning |
Author | Feng Wang, *Xiaoxia Wu, Yuan Xie (Pennsylvania State Univ., United States) |
Page | pp. 2 - 9 |
Detailed information (abstract, keywords, etc) |
Title | Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA |
Author | *Cheng-Tao Hsieh (Nat'l Tsing Hua Univ., Taiwan), Jason Cong, Zhiru Zhang (Univ. of California, Los Angeles, United States), Shih-Chieh Chang (Nat'l Tsing Hua Univ., Taiwan) |
Page | pp. 10 - 15 |
Detailed information (abstract, keywords, etc) |
Title | A Multicycle Communication Architecture and Synthesis Flow for Global Interconnect Resource Sharing |
Author | Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, *Ya-Shih Huang (Nat'l Chiao Tung Univ., Taiwan) |
Page | pp. 16 - 21 |
Detailed information (abstract, keywords, etc) |
Title | Scheduling with Integer Time Budgeting for Low-Power Optimization |
Author | Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, *Jason Cong (Univ. of California, Los Angeles, United States) |
Page | pp. 22 - 27 |
Detailed information (abstract, keywords, etc) |
Title | REWIRED - Register Write Inhibition by Resource Dedication |
Author | *Pushkar Tripathi, Rohan Jain (Indian Inst. of Tech. Delhi, India), Srikanth Kurra (Oracle, India), Preeti Ranjan Panda (Indian Inst. of Tech. Delhi, India) |
Page | pp. 28 - 31 |
Detailed information (abstract, keywords, etc) |
Title | An Efficient Performance Improvement Method Utilizing Specialized Functional Units in Behavioral Synthesis |
Author | *Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ., Japan) |
Page | pp. 32 - 35 |
Detailed information (abstract, keywords, etc) |
Title | Predictive Power Aware Management for Embedded Mobile Devices |
Author | *Young-Si Hwang, Sung-Kwan Ku, Chan-Min Jung, Ki-Seok Chung (Hanyang Univ., Republic of Korea) |
Page | pp. 36 - 41 |
Detailed information (abstract, keywords, etc) |
Title | A Dynamic-Programming Algorithm for Reducing the Energy Consumption of Pipelined System-Level Streaming Applications |
Author | N. Liveris, *H. Zhou (Northwestern Univ., United States), P. Banerjee (HP Labs, United States) |
Page | pp. 42 - 48 |
Detailed information (abstract, keywords, etc) |
Title | Temperature-Aware MPSoC Scheduling for Reducing Hot Spots and Gradients |
Author | *Ayse Kivilcim Coskun, Tajana Simunic Rosing (Univ. of California, San Diego, United States), Keith A. Whisnant, Kenny C. Gross (Sun Microsystems, United States) |
Page | pp. 49 - 54 |
Detailed information (abstract, keywords, etc) |
Title | Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing |
Author | *Hiroki Matsutani (Keio Univ., Japan), Michihiro Koibuchi (Nat'l Inst. of Informatics, Japan), Daihan Wang, Hideharu Amano (Keio Univ., Japan) |
Page | pp. 55 - 60 |
Detailed information (abstract, keywords, etc) |
Title | Automated Techniques for Energy Efficient Scheduling on Homogeneous and Heterogeneous Chip Multi-Processor Architectures |
Author | *Sushu Zhang, Karam S. Chatha (Arizona State Univ., United States) |
Page | pp. 61 - 66 |
Detailed information (abstract, keywords, etc) |
Title | Statistical Power Profile Correlation for Realistic Thermal Estimation |
Author | *Love Singhal (Univ. of California, Irvine, United States), Sejong Oh (KAIST, Republic of Korea), Eli Bozorgzadeh (Univ. of California, Irvine, United States) |
Page | pp. 67 - 70 |
Detailed information (abstract, keywords, etc) |
Title | Reconfigurable RTD-Based Circuit Elements of Complete Logic Functionality |
Author | *Yexin Zheng, Chao Huang (Virginia Tech., United States) |
Page | pp. 71 - 76 |
Detailed information (abstract, keywords, etc) |
Title | MBARC: A Scalable Memory Based Reconfigurable Computing Framework for Nanoscale Devices |
Author | Somnath Paul, *Swarup Bhunia (Case Western Reserve Univ., United States) |
Page | pp. 77 - 82 |
Detailed information (abstract, keywords, etc) |
Title | Moving Forward: A Non-Search Based Synthesis Method Toward Efficient CNOT-Based Quantum Circuit Synthesis Algorithms |
Author | *Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi (Amirkabir Univ. of Tech., Iran) |
Page | pp. 83 - 88 |
Detailed information (abstract, keywords, etc) |
Title | A CAD Tool for RF MEMS Devices |
Author | *Rajesh Pande, Rajendra Patrikar (Visvesvaraya Nat'l Inst. of Tech., India) |
Page | pp. 89 - 94 |
Detailed information (abstract, keywords, etc) |
Title | A 1.2GHz Delayed Clock Generator for High-speed Microprocessors |
Author | *Inhwa Jung, Moo-Young Kim, Chulwoo Kim (Korea Univ., Republic of Korea) |
Page | pp. 95 - 96 |
Detailed information (abstract, keywords, etc) |
Title | LVDS-Type On-Chip Transmision Line Interconnect with Passive Equalizers in 90 nm CMOS Process |
Author | *Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu (Tokyo Inst. of Tech., Japan) |
Page | pp. 97 - 98 |
Detailed information (abstract, keywords, etc) |
Title | A Slew-Rate Controlled Output Driver with One-Cycle Tuning Time |
Author | *Young-Ho Kwak, Inhwa Jung, Chulwoo Kim (Korea Univ., Republic of Korea) |
Page | pp. 99 - 100 |
Detailed information (abstract, keywords, etc) |
Title | A Low-Leakage Current Power 180-nm CMOS SRAM |
Author | *Tadayoshi Enomoto, Yuki Higuchi (Chuo Univ., Japan) |
Page | pp. 101 - 102 |
Detailed information (abstract, keywords, etc) |
Title | A CMOS Direct Sampling Mixer Using Switched Capacitor Filter Technique for Software-Defined Radio |
Author | *Hong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 103 - 104 |
Detailed information (abstract, keywords, etc) |
Title | Small-Area CMOS RF Distributed Mixer Using Multi-Port Inductors |
Author | *Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu (Tokyo Inst. of Tech., Japan) |
Page | pp. 105 - 106 |
Detailed information (abstract, keywords, etc) |
Title | Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification |
Author | *Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan) |
Page | pp. 107 - 108 |
Detailed information (abstract, keywords, etc) |
Title | Duo-Binary Circular Turbo Decoder Based on Border Metric Encoding for WiMAX |
Author | *Ji-Hoon Kim, In-Cheol Park (KAIST, Republic of Korea) |
Page | pp. 109 - 110 |
Detailed information (abstract, keywords, etc) |
Title | Area and Power Efficient Design of Coarse Time Synchronizer and Frequency Offset Estimator for Fixed WiMAX System |
Author | *Tae-Hwan Kim, In-Cheol Park (KAIST, Republic of Korea) |
Page | pp. 111 - 112 |
Detailed information (abstract, keywords, etc) |
Title | A Low-Cost Cryptographic Processor for Security Embedded System |
Author | *Ronghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, Lang Mai, Jia Zhao (Fudan Univ., China) |
Page | pp. 113 - 114 |
Detailed information (abstract, keywords, etc) |
Title | Multithreaded Coprocessor Interface for Multi-Core Multimedia SoC |
Author | *Shih Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih Wei Liu (Nat'l Chiao Tung Univ., Taiwan) |
Page | pp. 115 - 116 |
Detailed information (abstract, keywords, etc) |
Title | Parameterized Embedded In-circuit Emulator and Its Retargetable Debugging Software for Microprocessor/Microcontroller/DSP Processor |
Author | *Liang-Bi Chen, Yung-Chih Liu, Chien-Hung Chen, Chung-Fu Kao, Ing-Jer Huang (Nat'l Sun Yat-Sen Univ., Taiwan) |
Page | pp. 117 - 118 |
Detailed information (abstract, keywords, etc) |
Title | Global Optimization of Common Subexpressions for Multiplierless Synthesis of Multiple Constant Multiplications |
Author | Yuen-Hong Alvin Ho, Chi-Un Lei, *Hing-Kit Kwan, Ngai Wong (Univ. of Hong Kong, Hong Kong) |
Page | pp. 119 - 124 |
Detailed information (abstract, keywords, etc) |
Title | Decomposition Based Approach for Synthesis of Multi-Level Threshold Logic Circuits |
Author | Tejaswi Gowda, *Sarma Vrudhula (Arizona State Univ., United States) |
Page | pp. 125 - 130 |
Detailed information (abstract, keywords, etc) |
Title | Timing-Power Optimization for Mixed-Radix Ling Adders by Integer Linear Programming |
Author | *Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng (Univ. of California, San Diego, United States) |
Page | pp. 131 - 137 |
Detailed information (abstract, keywords, etc) |
Title | Efficient Synthesis of Compressor Trees on FPGAs |
Author | Hadi Parandeh-Afshar (Univ. of Tehran, Iran), *Philip Brisk, Paolo Ienne (EPFL, Switzerland) |
Page | pp. 138 - 143 |
Detailed information (abstract, keywords, etc) |
Title | Area Recovery under Depth Constraint by Cut Substitution for Technology Mapping for LUT-Based FPGAs |
Author | *Taiga Takata, Yusuke Matsunaga (Kyushu Univ., Japan) |
Page | pp. 144 - 147 |
Detailed information (abstract, keywords, etc) |
Title | An Optimal Algorithm for Sizing Sequential Circuits for Industrial Library Based Designs |
Author | Sanghamitra Roy, Yu Hen Hu (Univ. of Wisconsin, Madison, United States), *Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng (Nat'l Taiwan Univ., Taiwan) |
Page | pp. 148 - 151 |
Detailed information (abstract, keywords, etc) |
Title | Efficient Numerical Modeling of Random Rough Surface Effects for Interconnect Internal Impedance Extraction |
Author | *Quan Chen, Ngai Wong (Univ. of Hong Kong, Hong Kong) |
Page | pp. 152 - 157 |
Detailed information (abstract, keywords, etc) |
Title | Efficient Techniques for 3-D Impedance Extraction Using Mixed Boundary Element Method |
Author | *Fang Gong, Wenjian Yu, Zeyi Wang, Zhiping Yu (Tsinghua Univ., China), Changhao Yan (Fudan Univ., China) |
Page | pp. 158 - 163 |
Detailed information (abstract, keywords, etc) |
Title | Generating Stable and Sparse Reluctance/Inductance Matrix under Insufficient Conditions |
Author | *Yuichi Tanji (Kagawa Univ., Japan), Takayuki Watanabe (Univ. of Shizuoka, Japan), Hideki Asai (Shizuoka Univ., Japan) |
Page | pp. 164 - 169 |
Detailed information (abstract, keywords, etc) |
Title | Hierarchical Krylov Subspace Reduced Order Modeling of Large RLC Circuits |
Author | Duo Li, *Sheldon X.-D. Tan (Univ. of California, Riverside, United States) |
Page | pp. 170 - 175 |
Detailed information (abstract, keywords, etc) |
Title | Statistical Noise Margin Estimation for Sub-Threshold Combinational Circuits |
Author | *Yu Pu (Tech. Univ. Eindhoven, Netherlands), Jose Pineda de Gyvez (NXP Research Eindhoven, Netherlands), Henk Corporaal (Tech. Univ. Eindhoven, Netherlands), Yajun Ha (Nat'l Univ. of Singapore, Singapore) |
Page | pp. 176 - 179 |
Detailed information (abstract, keywords, etc) |
Title | Symmetry-Aware Placement with Transitive Closure Graphs for Analog Layout Design |
Author | *Lihong Zhang (Memorial Univ. of Newfoundland, Canada), C.-J. Richard Shi (Univ. of Washington, United States), Yingtao Jiang (Univ. of Nevada, United States) |
Page | pp. 180 - 185 |
Detailed information (abstract, keywords, etc) |
Title | Constraint-Free Analog Placement with Topological Symmetry Structure |
Author | *Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan) |
Page | pp. 186 - 191 |
Detailed information (abstract, keywords, etc) |
Title | TCG-Based Muli-Bend Bus Driven Floorplanning |
Author | Tilen Ma, *Evangeline F. Y. Young (The Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 192 - 197 |
Detailed information (abstract, keywords, etc) |
Title | Large-Scale Fixed-Outline Floorplanning Design Using Convex Optimization Techniques |
Author | *Chaomin Luo, Miguel F. Anjos (Univ. of Waterloo, Canada), Anthony Vannelli (Univ. of Guelph, Canada) |
Page | pp. 198 - 203 |
Detailed information (abstract, keywords, etc) |
Title | Bus-Aware Microarchitectural Floorplanning |
Author | Dae Hyun Kim, *Sung Kyu Lim (Georgia Inst. of Tech., United States) |
Page | pp. 204 - 208 |
Detailed information (abstract, keywords, etc) |
Title | LP Based White Space Redistribution for Thermal Via Planning and Performance Optimization in 3D ICs |
Author | *Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong (Tsinghua Univ., China), Jason Cong (Univ. of California, Los Angeles, United States) |
Page | pp. 209 - 212 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Predictive Models and CAD Methodology for Pattern Dependent Variability |
Author | *Nishath Verghese, Richard Rouse, Philippe Hurat (Cadence Design Systems, United States) |
Page | pp. 213 - 218 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Technology Modeling and Characterization Beyond the 45nm Node |
Author | *Sani R. Nassif (IBM, United States) |
Page | p. 219 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Synergistic Physical Synthesis for Manufacturability and Variability in 45nm Designs and Beyond |
Author | *David Z. Pan, Minsik Cho (Univ. of Texas, Austin, United States) |
Page | pp. 220 - 225 |
Detailed information (abstract, keywords, etc) |
Title | MaizeRouter: Engineering an Effective Global Router |
Author | *Michael D. Moffitt (IBM, United States) |
Page | pp. 226 - 231 |
Detailed information (abstract, keywords, etc) |
Title | A New Global Router for Modern Designs |
Author | *Jhih-Rong Gao, Pei-Ci Wu (Synopsys, Taiwan), Ting-Chi Wang (Nat'l Tsing Hua Univ., Taiwan) |
Page | pp. 232 - 237 |
Detailed information (abstract, keywords, etc) |
Title | Routability Driven Modification Method of Monotonic Via Assignment for 2-Layer Ball Grid Array Packages |
Author | *Yoichi Tomioka, Atsushi Takahashi (Tokyo Inst. of Tech., Japan) |
Page | pp. 238 - 243 |
Detailed information (abstract, keywords, etc) |
Title | Ordered Escape Routing Based on Boolean Satisfiability |
Author | Lijuan Luo, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, United States) |
Page | pp. 244 - 249 |
Detailed information (abstract, keywords, etc) |
Title | MeshWorks: An Efficient Framework for Planning, Synthesis and Optimization of Clock Mesh Networks |
Author | *Anand Rajaram, David Z. Pan (Univ. of Texas, Austin, United States) |
Page | pp. 250 - 257 |
Detailed information (abstract, keywords, etc) |
Title | Interconnect Modeling for Improved System-Level Design Optimization |
Author | Luca Carloni (Columbia Univ., United States), Andrew B. Kahng, Swamy Muddu (Univ. of California, San Diego, United States), Alessandro Pinto (Univ. of California, Berkeley, United States), *Kambiz Samadi, Puneet Sharma (Univ. of California, San Diego, United States) |
Page | pp. 258 - 264 |
Detailed information (abstract, keywords, etc) |
Title | NoCOUT : NoC Topology Generation with Mixed Packet-Switched and Point-to-Point Networks |
Author | Jeremy Chan, *Sri Parameswaran (Univ. of New South Wales, Australia) |
Page | pp. 265 - 270 |
Detailed information (abstract, keywords, etc) |
Title | Automatic Generation of Hardware dependent Software for MPSoCs from Abstract System Specifications |
Author | *Gunar Schirner, Andreas Gerstlauer, Rainer Dömer (Univ. of California, Irvine, United States) |
Page | pp. 271 - 276 |
Detailed information (abstract, keywords, etc) |
Title | Application-Specific Network-on-Chip Architecture Synthesis Based on Set Partitions and Steiner Trees |
Author | *Shan Yan, Bill Lin (Univ. of California, San Diego, United States) |
Page | pp. 277 - 282 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Floating-Point Reconfiguration Array Processor for 3D Graphics Physics Engine |
Author | *Hoonmo Yang (Core Logic, Republic of Korea) |
Page | p. 283 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Super-K: A SoC for Single-chip Ultra Mobile Computer |
Author | *Xu Cheng (Peking Univ., China) |
Page | p. 284 |
Detailed information (abstract, keywords, etc) |
Title | (Panel Discussion) The Tears and Joy of Sowing and Reaping Complex SoC's |
Author | Moderator: Ing-Jer Huang (Nat'l Sun Yat-Sen Univ., Taiwan), Panelists: Youn-Long Lin (Nat'l Tsing Hua Univ./Global UniChip, Taiwan), Hoonmo Yang (Core Logic, Republic of Korea), Toshihiro Hattori (Renesas, Japan), Ahmed Jarraya (CEA-LETI, MINATEC, France), Xu Chen (Peking Univ., China) |
Detailed information (abstract, keywords, etc) |
Wednesday, January 23, 2008 |
Title | (Keynote Address) The Evolution of SoC Platform According to the New Mobile Paradigm |
Author | Ki-Soo Hwang (Core Logic, Republic of Korea) |
Page | p. 285 |
Detailed information (abstract, keywords, etc) |
Title | Statistical Gate Delay Model for Multiple Input Switching |
Author | *Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ., Japan) |
Page | pp. 286 - 291 |
Detailed information (abstract, keywords, etc) |
Title | Non-Gaussian Statistical Timing Models of Die-to-Die and Within-Die Parameter Variations for Full Chip Analysis |
Author | *Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya (Fujitsu Labs., Japan) |
Page | pp. 292 - 297 |
Detailed information (abstract, keywords, etc) |
Title | Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting |
Author | Lerong Cheng (Univ. of California, Los Angeles, United States), *Jinjun Xiong (IBM, United States), Lei He (Univ. of California, Los Angeles, United States) |
Page | pp. 298 - 303 |
Detailed information (abstract, keywords, etc) |
Title | A Capacitive Boosted Buffer Technique for High-Speed Process-Variation-Tolerant Interconnect in UDVS Application |
Author | Saihua Lin, *Yu Wang, Rong Luo, Huazhong Yang (Tsinghua Univ., China) |
Page | pp. 304 - 309 |
Detailed information (abstract, keywords, etc) |
Title | Static Timing: Back to Our Roots |
Author | Ruiming Chen, Lizheng Zhang, Vladimir Zolotov, Chandu Visweswariah, *Jinjun Xiong (IBM, United States) |
Page | pp. 310 - 315 |
Detailed information (abstract, keywords, etc) |
Title | Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-Addressable Memory Using Gate-Block Selection Algorithm |
Author | *Jui-Yuan Hsieh, Shanq-Jang Ruan (Nat'l Taiwan Univ. of Science and Tech., Taiwan) |
Page | pp. 316 - 321 |
Detailed information (abstract, keywords, etc) |
Title | Block Cache for Embedded Systems |
Author | *Dominic Hillenbrand, Jörg Henkel (Univ. of Karlsruhe (TH), Germany) |
Page | pp. 322 - 327 |
Detailed information (abstract, keywords, etc) |
Title | A Compiler-in-the-Loop Framework to Explore Horizontally Partitioned Cache Architectures |
Author | *Aviral Shrivastava (Arizona State Univ., United States), Ilya Issenin, Nikil Dutt (Univ. of California, Irvine, United States) |
Page | pp. 328 - 333 |
Detailed information (abstract, keywords, etc) |
Title | Fast, Quasi-Optimal, and Pipelined Instruction-Set Extensions |
Author | *Ajay K. Verma, Philip Brisk, Paolo Ienne (EPFL, Switzerland) |
Page | pp. 334 - 339 |
Detailed information (abstract, keywords, etc) |
Title | Load Scheduling: Reducing Pressure on Distributed Register Files for Free |
Author | *Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang (Nat'l Univ. of Defense Tech., China) |
Page | pp. 340 - 345 |
Detailed information (abstract, keywords, etc) |
Title | DPlace2.0: A Stable and Efficient Analytical Placement Based on Diffusion |
Author | Tao Luo, *David Z. Pan (Univ. of Texas, Austin, United States) |
Page | pp. 346 - 351 |
Detailed information (abstract, keywords, etc) |
Title | Total Power Optimization Combining Placement, Sizing and Multi-Vt Through Slack Distribution Management |
Author | Tao Luo (Univ. of Texas, Austin, United States), David Newmark (Advanced Micro Devices, United States), *David Z. Pan (Univ. of Texas, Austin, United States) |
Page | pp. 352 - 357 |
Detailed information (abstract, keywords, etc) |
Title | An Innovative Steiner Tree Based Approach for Polygon Partitioning |
Author | Yongqiang Lu, *Qing Su, Jamil Kawa (Synopsys, United States) |
Page | pp. 358 - 363 |
Detailed information (abstract, keywords, etc) |
Title | An MILP-Based Wire Spreading Algorithm for PSM-Aware Layout Modification |
Author | *Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang (Nat'l Tsing Hua Univ., Taiwan) |
Page | pp. 364 - 369 |
Detailed information (abstract, keywords, etc) |
Title | Low Power Clock Buffer Planning Methodology in F-D Placement for Large Scale Circuit Design |
Author | *Yanfeng Wang, Qiang Zhou, Yici Cai (Tsinghua Univ., China), Jiang Hu (Texas A&M Univ., United States), Xianlong Hong, Jinian Bian (Tsinghua Univ., China) |
Page | pp. 370 - 375 |
Detailed information (abstract, keywords, etc) |
Title | Power Grid Analysis Benchmarks |
Author | *Sani R. Nassif (IBM, United States) |
Page | pp. 376 - 381 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) In-band Mobile Digital TV Transmission Technology for Advanced Television Systems Committee |
Author | *Junehee Lee (Samsung Electronics, Republic of Korea) |
Page | p. 382 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) In-Vehicle Vision Processors for Driver Assistance Systems |
Author | *Shorin Kyo, Shin’ichiro Okazaki (NEC, Japan) |
Page | pp. 383 - 388 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Multi-Core DSP for Base Stations: Large and Small |
Author | *Doug Pulley (picoChip, Great Britain) |
Page | pp. 389 - 391 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) 1-cc Computer Using UWB-IR for Wireless Sensor Network |
Author | *Tatsuo Nakagawa, Masayuki Miyazaki, Goichi Ono, Ryosuke Fujiwara, Takayasu Norimatsu, Takahide Terada (Hitachi, Japan), Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura (YRP Ubiquitous Networking Lab., Japan) |
Page | pp. 392 - 397 |
Detailed information (abstract, keywords, etc) |
Title | Verifying Full-Custom Multipliers by Boolean Equivalence Checking and an Arithmetic Bit Level Proof |
Author | *Udo Krautz, Markus Wedler, Wolfgang Kunz (Univ. Kaiserslautern, Germany), Kai Weber, Christian Jacobi, Matthias Pflanz (IBM, Germany) |
Page | pp. 398 - 403 |
Detailed information (abstract, keywords, etc) |
Title | A Symbolic Approach for Mixed-Signal Model Checking |
Author | *Alexander Jesser, Lars Hedrich (Univ. of Frankfurt a.M., Germany) |
Page | pp. 404 - 409 |
Detailed information (abstract, keywords, etc) |
Title | Faster Projection Based Methods for Circuit Level Verification |
Author | *Chao Yan, Mark Greenstreet (Univ. of British Columbia, Canada) |
Page | pp. 410 - 415 |
Detailed information (abstract, keywords, etc) |
Title | A Debug Probe for Concurrently Debugging Multiple Embedded Cores and Inter-Core Transactions in NoC-Based Systems |
Author | Shan Tang, *Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 416 - 421 |
Detailed information (abstract, keywords, etc) |
Title | A Fast Two-Pass HDL Simulation with On-Demand Dump |
Author | *Kyuho Shim (Pusan Nat'l Univ., Republic of Korea), Youngrae Cho, Namdo Kim (Samsung Electronics, Republic of Korea), Hyuncheol Baik, Kyungkuk Kim, Dusung Kim (Pusan Nat'l Univ., Republic of Korea), Jaebum Kim, Byeongun Min, Kyumyung Choi (Samsung Electronics, Republic of Korea), Maciej Ciesielski (Logic-Mill Technology LLC, United States), Seiyang Yang (Pusan Nat'l Univ., Republic of Korea) |
Page | pp. 422 - 427 |
Detailed information (abstract, keywords, etc) |
Title | Hybrid Solid-State Disks: Combining Heterogeneous NAND Flash in Large SSDs |
Author | *Li-Pin Chang (Nat'l Chiao Tung Univ., Taiwan) |
Page | pp. 428 - 433 |
Detailed information (abstract, keywords, etc) |
Title | Enabling Run-Time Memory Data Transfer Optimizations at the System Level with Automated Extraction of Embedded Software Metadata Information |
Author | *Alexandros Bartzas (Democritus Univ. of Thrace, Greece), Miguel Peon-Quiros (Univ. Complutense de Madrid, Spain), Stylianos Mamagkakis, Francky Catthoor (IMEC vzw, Belgium), Dimitrios Soudris (Democritus Univ. of Thrace, Greece), Jose Manuel Mendias (Univ. Complutense de Madrid, Spain) |
Page | pp. 434 - 439 |
Detailed information (abstract, keywords, etc) |
Title | Automatic Re-Coding of Reference Code into Structured and Analyzable SoC Models |
Author | Pramod Chandraiah, *Rainer Dömer (Univ. of California, Irvine, United States) |
Page | pp. 440 - 445 |
Detailed information (abstract, keywords, etc) |
Title | Action Coverage Formulation for Power Optimization in Body Sensor Networks |
Author | Hassan Ghasemzadeh, *Eric Guenterberg, Katherine Gilani, Roozbeh Jafari (Univ. of Texas, Dallas, United States) |
Page | pp. 446 - 451 |
Detailed information (abstract, keywords, etc) |
Title | Dynamic Scheduling of Imprecise-Computation Tasks in Maximizing QoS under Energy Constraints for Embedded Systems |
Author | *Heng Yu, Bharadwaj Veeravalli, Yajun Ha (Nat'l Univ. of Singapore, Singapore) |
Page | pp. 452 - 455 |
Detailed information (abstract, keywords, etc) |
Title | Architecture-level Thermal Behavioral Characterization For Multi-Core Microprocessors |
Author | Duo Li, *Sheldon X.-D. Tan (Univ. of California, Riverside, United States), Murli Tirumala (Intel, United States) |
Page | pp. 456 - 461 |
Detailed information (abstract, keywords, etc) |
Title | Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms |
Author | *Pei-Yu Huang, Chih-Kang Lin, Yu-Min Lee (Nat'l Chiao Tung Univ., Taiwan) |
Page | pp. 462 - 467 |
Detailed information (abstract, keywords, etc) |
Title | A Stochastic Local Hot Spot Alerting Technique |
Author | Hwisung Jung, *Massoud Pedram (Univ. of Southern California, United States) |
Page | pp. 468 - 473 |
Detailed information (abstract, keywords, etc) |
Title | Design Rule Optimization of Regular layout for Leakage Reduction in Nanoscale Design |
Author | Anupama R. Subramaniam, Ritu Singhal, *Chi-Chao Wang, Yu Cao (Arizona State Univ., United States) |
Page | pp. 474 - 479 |
Detailed information (abstract, keywords, etc) |
Title | Investigation of Diffusion Rounding for Post-Lithography Analysis |
Author | Puneet Gupta (Univ. of California, Los Angles, United States), Andrew B. Kahng (Univ. of California, San Diego, United States), *Youngmin Kim (Univ. of Michigan, Ann Arbor, United States), Saumil Shah (Blaze-DFM, United States), Dennis Sylvester (Univ. of Michigan, Ann Arbor, United States) |
Page | pp. 480 - 485 |
Detailed information (abstract, keywords, etc) |
Title | (Panel Discussion) Are System Level EDA Tools/Methodologies Coming? |
Author | Moderator: Ren-Song Tsay (Nat l Tsing Hua Univ., Taiwan), Panelists: Raul Camposano (Xoomsys, Tajikistan), Toshihiro Hattori (Renesas, Japan), Austin Kim (Samsung Electronics, Republic of Korea), Howard Mao (Springsoft, Taiwan), Sri Parameswaran (Univ. of New South Wales, Australia) |
Detailed information (abstract, keywords, etc) |
Title | Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering |
Author | *Debasish Das (Northwestern Univ., United States), Kip Killpack, Chandramouli Kashyap, Abhijit Jas (Intel, United States), Hai Zhou (Northwestern Univ., United States) |
Page | pp. 486 - 491 |
Detailed information (abstract, keywords, etc) |
Title | A Fast Incremental Clock Skew Scheduling Algorithm for Slack Optimization |
Author | *Kui Wang, Hao Fang, Hu Xu, Xu Cheng (Peking Univ., China) |
Page | pp. 492 - 497 |
Detailed information (abstract, keywords, etc) |
Title | Clock Tree Synthesis with Data-Path Sensitivity Matching |
Author | *Matthew R. Guthaus (Univ. of California Santa Cruz, United States), Dennis Sylvester (Univ. of Michigan, United States), Richard B. Brown (Univ. of Utah, United States) |
Page | pp. 498 - 503 |
Detailed information (abstract, keywords, etc) |
Title | Buffered Clock Tree Synthesis for 3D ICs Under Thermal Variations |
Author | Jacob Minz (Synopsys, United States), Xin Zhao, *Sung Kyu Lim (Georgia Inst. of Tech., United States) |
Page | pp. 504 - 509 |
Detailed information (abstract, keywords, etc) |
Title | A Delay Model for Interconnect Trees Based on ABCD Matrix |
Author | *Guofei Zhou, Li Su, Depeng Jin, Lieguang Zeng (Tsinghua Univ., China) |
Page | pp. 510 - 513 |
Detailed information (abstract, keywords, etc) |
Title | Analytical Model for the Impact of Multiple Input Switching Noise on Timing |
Author | Rajeshwary Tayade (Univ. of Texas, Austin, United States), *Sani Nassif (IBM, United States), Jacob Abraham (Univ. of Texas, Austin, United States) |
Page | pp. 514 - 517 |
Detailed information (abstract, keywords, etc) |
Title | Determination of Optimal Polynomial Regression Function to Decompose On-Die Systematic and Random Variations |
Author | *Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu (Tokyo Inst. of Tech., Japan) |
Page | pp. 518 - 523 |
Detailed information (abstract, keywords, etc) |
Title | Within-Die Process Variations: How Accurately Can They Be Statistically Modeled? |
Author | Brendan Hargreaves, Henrik Hult, *Sherief Reda (Brown Univ., United States) |
Page | pp. 524 - 530 |
Detailed information (abstract, keywords, etc) |
Title | Chebyshev Affine Arithmetic Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty |
Author | Jin Sun, Yue Huang (Univ. of Arizona, United States), Jun Li (Anova Solutions, United States), *Janet M. Wang (Univ. of Arizona, United States) |
Page | pp. 531 - 536 |
Detailed information (abstract, keywords, etc) |
Title | Distribution Arithmetic for Stochastical Analysis |
Author | *Markus Olbrich, Erich Barke (Univ. of Hannover, Germany) |
Page | pp. 537 - 542 |
Detailed information (abstract, keywords, etc) |
Title | Handling Partial Correlations in Yield Prediction |
Author | Sridhar Varadan (Texas A&M Univ., United States), *Janet Wang (Univ. of Arizona, United States), Jiang Hu (Texas A&M Univ., United States) |
Page | pp. 543 - 548 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Reliability-Aware Design for Nanometer-Scale Devices |
Author | *David Atienza (EPFL, Swaziland), Giovanni De Micheli (LSI/EPFL, Swaziland), Luca Benini (DEIS/UNIBO, Italy), José L. Ayala, Pablo G. Del Valle (DACYA/UCM, Spain), Michael DeBole, Vijay Narayanan (CSE/PSU, United States) |
Page | pp. 549 - 554 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) An Industrial Perspective of Power-aware Reliable SoC Design |
Author | *Soo-Kwan Eo, Sungjoo Yoo, Kyu-Myung Choi (Samsung Electronics, Republic of Korea) |
Page | pp. 555 - 557 |
Detailed information (abstract, keywords, etc) |
Title | (Panel Discussion) How to Design Cool Chips for Hot Products |
Author | Moderator: Massoud Pedram (Univ. of Southern California, United States), Panelists: Giovanni De Micheli (EPFL, Swaziland), Jan Rabaey (Univ. of California, Berkeley, United States), Sookwan Eo (Samsung Electronics, Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Thursday, January 24, 2008 |
Title | (Keynote Address) The Future of Semiconductor Industry - A Foundry's Perspective |
Author | *F. C. Tseng (TSMC, Taiwan) |
Page | p. 558 |
Detailed information (abstract, keywords, etc) |
Title | Soft Error Rate Reduction Using Redundancy Addition and Removal |
Author | *Kai-Chiang Wu, Diana Marculescu (Carnegie Mellon Univ., United States) |
Page | pp. 559 - 564 |
Detailed information (abstract, keywords, etc) |
Title | Localized Random Access Scan: Towards Low Area and Routing Overhead |
Author | *Yu Hu, Xiang Fu, Xiaoxin Fan (Chinese Academy of Sciences, China), Hideo Fujiwara (NAIST, Japan) |
Page | pp. 565 - 570 |
Detailed information (abstract, keywords, etc) |
Title | A Design-for-Diagnosis Technique for Diagnosing Both Scan Chain Faults and Combinational Circuit Faults |
Author | Fei Wang, *Yu Hu, Huawei Li, Xiaowei Li (Chinese Academy of Sciences, China) |
Page | pp. 571 - 576 |
Detailed information (abstract, keywords, etc) |
Title | GECOM: Test Data Compression Combined with All Unknown Response Masking |
Author | *Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan) |
Page | pp. 577 - 582 |
Detailed information (abstract, keywords, etc) |
Title | Mixed Integer Linear Programming-Based Optimal Topology Synthesis of Cascaded Crossbar Switches |
Author | *Minje Jun (Yonsei Univ., Republic of Korea), Sungjoo Yoo (Samsung Electronics, Republic of Korea), Eui-Young Chung (Yonsei Univ., Republic of Korea) |
Page | pp. 583 - 588 |
Detailed information (abstract, keywords, etc) |
Title | Automatic Interface Synthesis Based on the Classification of Interface Protocols of IPs |
Author | *ChangRyul Yun (Agency for Defense Development, Republic of Korea), DongSoo Kang (Chungnam Nat'l Univ., Republic of Korea), YoungHwan Bae, HanJin Cho (ETRI, Republic of Korea), KyoungSon Jhang (Chungnam Nat'l Univ., Republic of Korea) |
Page | pp. 589 - 594 |
Detailed information (abstract, keywords, etc) |
Title | The Shining Embedded System Design Methodology Based on Self Dynamic Reconfigurable Architectures |
Author | C. A. Curino, *L. Fossati, V. Rana, F. Redaelli, M. D. Santambrogio, D. Sciuto (Politecnico di Milano, Italy) |
Page | pp. 595 - 600 |
Detailed information (abstract, keywords, etc) |
Title | Robust On-Chip Bus Architecture Synthesis for MPSoC Under Random Tasks Arrival |
Author | *Sujan Pandey (NXP Semiconductors Research, Netherlands), Rolf Drechsler (Univ. of Bremen, Germany) |
Page | pp. 601 - 606 |
Detailed information (abstract, keywords, etc) |
Title | A Multi-Processor NoC Platform Applied on the 802.11i TKIP Cryptosystem |
Author | *Jung-Ho Lee, Sung-Rok Yoon, Kwang-Eui Pyun, Sin-Chong Park (ICU, Republic of Korea) |
Page | pp. 607 - 610 |
Detailed information (abstract, keywords, etc) |
Title | A Unified Methodology for Power Supply Noise Reduction in Modern Microarchitecture Design |
Author | Michael Healy, Fayez Mohamood, Hsien-Hsin S. Lee, *Sung Kyu Lim (Georgia Inst. of Tech., United States) |
Page | pp. 611 - 616 |
Detailed information (abstract, keywords, etc) |
Title | Heuristic Power/Ground Network and Floorplan Co-Design Method |
Author | *Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong (Tsinghua Univ., China) |
Page | pp. 617 - 622 |
Detailed information (abstract, keywords, etc) |
Title | Vertical Via Design Techniques for Multi-Layered P/G Networks |
Author | *Shuai Li, Jin Shi, Yici Cai, Xianlong Hong (Tsinghua Univ., China) |
Page | pp. 623 - 628 |
Detailed information (abstract, keywords, etc) |
Title | Statistical Mixed Vt Allocation of Body-Biased Circuits for Reduced Leakage Variation |
Author | Jinseob Jeong, *Seungwhun Paik, Youngsoo Shin (KAIST, Republic of Korea) |
Page | pp. 629 - 634 |
Detailed information (abstract, keywords, etc) |
Title | Exploring High-Speed Low-Power Hybrid Arithmetic Units at Scaled Supply and Adaptive Clock-Stretching |
Author | Swaroop Ghosh, *Kaushik Roy (Purdue Univ., United States) |
Page | pp. 635 - 640 |
Detailed information (abstract, keywords, etc) |
Title | (Panel Discussion) Concurrent SoC and SiP Designs |
Author | Moderator: Wei-Chung Lo (ITRI, Taiwan), Panelists: C. P. Hung (ASE, Taiwan), Lung Chu (Cadence Design Systems, United States), Joungho Kim (KAIST, Republic of Korea), Epan Wu (VIA Technologies, Taiwan) |
Detailed information (abstract, keywords, etc) |
Title | Circuit Lines for Guiding the Generation of Random Test Sequences for Synchronous Sequential Circuits |
Author | Irith Pomeranz (Purdue Univ., United States), *Sudhakar M. Reddy (Univ. of Iowa, United States) |
Page | pp. 641 - 646 |
Detailed information (abstract, keywords, etc) |
Title | A New Low Energy BIST Using A Statistical Code |
Author | *Sunghoon Chun, Taejin Kim, Sungho Kang (Yonsei Univ., Republic of Korea) |
Page | pp. 647 - 652 |
Detailed information (abstract, keywords, etc) |
Title | On Reducing Both Shift and Capture Power for Scan-Based Testing |
Author | Jia Li (Chinese Academy of Sciences, China), *Qiang Xu (The Chinese Univ. of Hong Kong, Hong Kong), Yu Hu, Xiaowei Li (Chinese Academy of Sciences, China) |
Page | pp. 653 - 658 |
Detailed information (abstract, keywords, etc) |
Title | Robust Test Generation for Power Supply Noise Induced Path Delay Faults |
Author | *Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li (Chinese Academy of Sciences, China) |
Page | pp. 659 - 662 |
Detailed information (abstract, keywords, etc) |
Title | Test Vector Chains for Increased Targeted and Untargeted Fault Coverage |
Author | Irith Pomeranz (Purdue Univ., United States), *Sudhakar M. Reddy (Univ. of Iowa, United States) |
Page | pp. 663 - 666 |
Detailed information (abstract, keywords, etc) |
Title | Parallel Fault Backtracing for Calculation of Fault Coverage |
Author | *Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman (Tallinn Univ. of Tech., Estonia) |
Page | pp. 667 - 672 |
Detailed information (abstract, keywords, etc) |
Title | ReSP: A Non-Intrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration |
Author | Giovanni Beltrame (European Space Agency, Netherlands), Cristiana Bolchini, *Luca Fossati, Antonio Miele, Donatella Sciuto (Politecnico di Milano, Italy) |
Page | pp. 673 - 678 |
Detailed information (abstract, keywords, etc) |
Title | Collaborative Hardware/Software Partition of Coarse-Grained Reconfigurable System Using Evolutionary Ant Colony Optimization |
Author | *Dawei Wang, Sikun Li, Yong Dou (Nat'l Univ. of Defense Tech., China) |
Page | pp. 679 - 684 |
Detailed information (abstract, keywords, etc) |
Title | Design Space Exploration for a Coarse Grain Accelerator |
Author | *Farhad Mehdipour, Hamid Noori (Kyushu Univ., Japan), Morteza Saheb Zamani (Amirkabir Univ. of Tech., Iran), Koji Inoue, Kazuaki Murakami (Kyushu Univ., Japan) |
Page | pp. 685 - 690 |
Detailed information (abstract, keywords, etc) |
Title | Efficient Symbolic Multi–Objective Design Space Exploration |
Author | *Martin Lukasiewycz, Michael Glaβ, Christian Haubelt, Jürgen Teich (Univ. of Erlangen-Nuremberg, Germany) |
Page | pp. 691 - 696 |
Detailed information (abstract, keywords, etc) |
Title | Scalable Unified Dual-Radix Architecture for Montgomery Multiplication in GF(P) and GF(2n) |
Author | *Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan) |
Page | pp. 697 - 702 |
Detailed information (abstract, keywords, etc) |
Title | Optimal Allocation and Placement of Thermal Sensors for Reconfigurable Systems and Its Practical Extension |
Author | *ByungHyun Lee, Taewhan Kim (Seoul Nat'l Univ., Republic of Korea) |
Page | pp. 703 - 707 |
Detailed information (abstract, keywords, etc) |
Title | Exploring Power Management in Multi-Core Systems |
Author | Reinaldo Bergamaschi (IBM, United States), Guoling Han (Univ. of California, Los Angeles, United States), Alper Buyuktosunoglu (IBM, United States), Hiren Patel (Virginia Tech, United States), Indira Nair, *Gero Dittmann, Geert Janssen, Nagu Dhanwada, Zhigang Hu, Pradip Bose, John Darringer (IBM, United States) |
Page | pp. 708 - 713 |
Detailed information (abstract, keywords, etc) |
Title | Dependability, Power, and Performance Trade-Off on a Multicore Processor |
Author | *Toshinori Sato (Kyushu Univ., Japan), Toshimasa Funaki (Kyushu Inst. of Tech., Japan) |
Page | pp. 714 - 719 |
Detailed information (abstract, keywords, etc) |
Title | High Performance Current-Mode Differential Logic |
Author | Ling Zhang (Univ. of California, San Diego, United States), Jianhua Liu (Altera, United States), Haikun Zhu (Qualcomm, United States), *Chung-Kuan Cheng (Univ. of California, San Diego, United States), Masanori Hashimoto (Osaka Univ., Japan) |
Page | pp. 720 - 725 |
Detailed information (abstract, keywords, etc) |
Title | NBTI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution? |
Author | Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, *Kaushik Roy (Purdue Univ., United States) |
Page | pp. 726 - 731 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Reaching the Limits of Low Power Design |
Author | J. S. Hobbs, *T. W. Williams (Synopsys, United States) |
Page | pp. 732 - 735 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Software-Cooperative Power-Efficient Heterogeneous Multi-Core for Media Processing |
Author | *Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka (Hitachi, Japan), Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ., Japan) |
Page | pp. 736 - 741 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Experiences of Low Power Design Implementation and Verification |
Author | *Shi-Hao Chen, Jiing-Yuan Lin (Global Unichip, Taiwan) |
Page | pp. 742 - 747 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Low Power Architecture and Design Techniques for Mobile Handset LSI Medity™ M2 |
Author | *Shuichi Kunie, Takefumi Hiraga, Tatsuya Tokue, Sunao Torii, Taku Ohsawa (NEC, Japan) |
Page | pp. 748 - 753 |
Detailed information (abstract, keywords, etc) |
Title | An Efficient, Fully Nonlinear, Variability-Aware Non-Monte-Carlo Yield Estimation Procedure with Applications to SRAM Cells and Ring Oscillators |
Author | *Chenjie Gu, Jaijeet Roychowdhury (Univ. of Minnesota, United States) |
Page | pp. 754 - 761 |
Detailed information (abstract, keywords, etc) |
Title | Analog Circuit Simulation Using Range Arithmetics |
Author | *Darius Grabowski, Markus Olbrich, Erich Barke (Univ. of Hannover, Germany) |
Page | pp. 762 - 767 |
Detailed information (abstract, keywords, etc) |
Title | LTCC Spiral Inductor Modeling, Synthesis, and Optimization |
Author | *Tuck-Boon Chan, Hsin-Chia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen (Nat'l Taiwan Univ., Taiwan) |
Page | pp. 768 - 771 |
Detailed information (abstract, keywords, etc) |
Title | Symmetry Constraint based on Mismatch Analysis for Analog Layout in SOI Technology |
Author | *Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He (Tsinghua Univ., China), Satoshi Goto (Waseda Univ., Japan) |
Page | pp. 772 - 775 |
Detailed information (abstract, keywords, etc) |
Title | SPKM : A Novel Graph Drawing Based Algorithm for Application Mapping onto Coarse-Grained Reconfigurable Architectures |
Author | *Jonghee Yoon (Seoul Nat'l Univ., Republic of Korea), Aviral Shrivastava (Arizona State Univ., United States), Sanghyun Park, Minwook Ahn (Seoul Nat'l Univ., Republic of Korea), Reiley Jeyapaul (Arizona State Univ., United States), Yunheung Paek (Seoul Nat'l Univ., Republic of Korea) |
Page | pp. 776 - 782 |
Detailed information (abstract, keywords, etc) |
Title | Block Remap with Turnoff: A Variation-Tolerant Cache Design Technique |
Author | *Mohammed Abid Hussain (Int'l Inst. of Information Tech., Hyderabad, India), Madhu Mutyam (Indian Inst. of Tech. Madras, India) |
Page | pp. 783 - 788 |
Detailed information (abstract, keywords, etc) |
Title | ORB: An On-Chip Optical Ring Bus Communication Architecture for Multi-Processor Systems-on-Chip |
Author | *Sudeep Pasricha, Nikil Dutt (Univ. of California, Irvine, United States) |
Page | pp. 789 - 794 |
Detailed information (abstract, keywords, etc) |
Title | Webpage-Based Benchmarks for Mobile Device Design |
Author | *Marc Somers, JoAnn M. Paul (Virginia Tech., United States) |
Page | pp. 795 - 800 |
Detailed information (abstract, keywords, etc) |
Title | (Panel Discussion) Best Ways to Use Billions of Devices on a Chip |
Author | Moderator: Grant Martin (Tensilica, United States), Panelists: Deming Chen (Univ. of Illinois, Urbana-Champaign, United States), Nikil Dutt (Univ. of California, Irvine, United States), Joerg Henkel (Karlsruhe Univ., Germany), Kyungho Kim (Samsung Electronics, Republic of Korea), Kazutoshi Kobayashi (Kyoto Univ., Japan) |
Page | pp. 801 - 802 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip |
Author | Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, *Deming Chen (Univ. of Illinois, Urbana-Champaign, United States) |
Page | pp. 803 - 808 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Quo Vadis, BTSoC (Billion Transistor SoC)? |
Author | *Nikil Dutt (Univ. of California, Irvine, United States) |
Page | p. 809 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Best Ways to use Billions of Devices on a Wireless Mobile SoC |
Author | *KyungHo Kim (Samsung Electronics, Republic of Korea) |
Page | p. 810 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Best Ways to Use Billions of Devices on a Chip - Error Predictive, Defect Tolerant and Error Recovery Designs |
Author | *Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan) |
Page | pp. 811 - 812 |
Detailed information (abstract, keywords, etc) |