Program at a Glance Designers' Forum


Full Day 1
System-Level Synthesis: Functions, Architectures, and Communications
Alberto Sangiovanni Vincentelli, UC Berkeley
Jason Cong, UCLA
Radu Marculescu, CMU
Clas A. Jacobson, United Technologies

Full Day 2
Cross-Layer Approaches to Designing Reliable Systems using Unreliable Chips
Nikil Dutt, Fadi Kurdahi, Ahmed Eltawil (UCI), Sani Nassif, IBM

Half Day 1
Latest Advances and Future Opportunities on CAD for FPGAs
Deming Chen, Martin D.F. Wong, UIUC

Half Day 2
Improvements in 65/45nm Physical Implementation Flow and Methodology
Andrew B. Kahng, UCSD

Half Day 3
Communication Performance in NOCs and Industry Experiences
David Gwilt, ARM
Axel Jantsch, KTH

Half Day 4
Verification of Multi-voltage ICs
Richard Rader, Samsung Electronics