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The 14th Asia and South Pacific Design Automation Conference

Session 1A  On-Chip Communication Architectures
Time: 10:15 - 12:20 Tuesday, January 20, 2009
Location: Room 411+412
Chair: Sri Parameswaran (Univ. of New South Wales, Australia)

1A-1 (Time: 10:15 - 10:40)
TitleAdaptive Inter-router Links for Low-Power, Area-Efficient and Reliable Network-on-Chip (NoC) Architectures
AuthorAvinash Karanth Kodi (Ohio Univ., United States), Ashwini Sarathy, Ahmed Louri, *Janet Wang (Univ. of Arizona, United States)
Pagepp. 1 - 6
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1A-2 (Time: 10:40 - 11:05)
TitleAnalysis of Communication Delay Bounds for Network on Chips
Author*Yue Qian (National Univ. of Defense Tech., China), Zhonghai Lu (Royal Inst. of Tech., Sweden), Wenhua Dou (National Univ. of Defense Tech., China)
Pagepp. 7 - 12
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1A-3 (Time: 11:05 - 11:30)
TitleFrequent Value Compression in Packet-based NoC Architectures
AuthorPing Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, *Jun Yang (Univ. of Pittsburgh, United States), Li Zhao (Intel, United States)
Pagepp. 13 - 18
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1A-4 (Time: 11:30 - 11:55)
TitleSimultaneous Data Transfer Routing and Scheduling for Interconnect Minimization in Multicycle Communication Architecture
AuthorYu-Ju Hong (Purdue Univ., United States), Ya-Shih Huang, *Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Pagepp. 19 - 24
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1A-5 (Time: 11:55 - 12:20)
TitleDynamically Reconfigurable On-Chip Communication Architectures for Multi Use-Case Chip Multiprocessor Applications
AuthorSudeep Pasricha, *Nikil Dutt, Fadi Kurdahi (Univ. of California, Irvine, United States)
Pagepp. 25 - 30
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