| Title | FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization |
| Author | *Gregory Lucas, Scott Cromar, Deming Chen (University of Illinois, Urbana-Champaign, United States) |
| Page | pp. 61 - 66 |
| Keyword | high level synthesis, process variation, ssta |
| Abstract | We propose a new variation-aware high-level synthesis binding/module selection algorithm, named FastYield, that takes into consideration multiplexers, functional units, registers, and interconnects. Additionally, FastYield connects with the lower levels of the design hierarchy through its inclusion of a timing driven floorplanner guided by a statistical static timing analysis (SSTA) engine which is used to modify/enhance the synthesis solution. On average, FastYield achieves an 85% performance yield clock period that is 14.5% smaller, and a performance yield gain of 78.9%, when compared to a variation-unaware algorithm. |
| Title | CriAS: A Performance-Driven Criticality-Aware Synthesis Flow for On-Chip Multicycle Communication Architecture |
| Author | *Chia-I Chen, Juinn-Dar Huang (National Chiao Tung University, Taiwan) |
| Page | pp. 67 - 72 |
| Keyword | Architectural synthesis, multicycle communication architecture, distributed register architecture, criticality-aware, performance-driven |
| Abstract | In deep submicron era, wire delay is no longer negligible and is dominating the system performance. Several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures to cope with the increasing wire delay by allowing on-chip multicycle communication. In this paper, we present a new performance-driven criticality-aware synthesis flow CriAS targeting regular distributed register architectures. CriAS features a hierarchical binding strategy and a coarse-grained placer for minimizing the number of critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that 19% overall performance improvement can be achieved on average as compared to the previous work. |
| Title | Tolerating Process Variations in High-Level Synthesis Using Transparent Latches |
| Author | *Yibo Chen, Yuan Xie (the Pennsylvania State University, United States) |
| Page | pp. 73 - 78 |
| Keyword | high-level synthesis, process variation, latch |
| Abstract | Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced control steps and reducing the attainable frequency of the circuit. To tackle this problem, this paper proposes a methodology to replace the edge-trigged flip-flops by transparent latches, to exploit latches' extra ability of passing time slacks and tolerating delay variations. In the paper we first define the timing yield in high-level synthesis, and then present how to replace flip-flops with latches to improve timing yield and mitigate the impact of process variations. We then discuss the benefits and overheads for the replacement, and propose an optimization framework for latch replacement in high-level synthesis design flow. Experimental results show that the latch-based design can achieve an average of 27% improvement of timing yield compared with traditional flip-flop based design. |
| Title | Variation-Aware Resource Sharing and Binding in Behavioral Synthesis |
| Author | Feng Wang (Qualcomm Inc., United States), Yuan Xie (Pennsylvania State University, United States), *Andres Takach (Mentor Graphics Corporation, United States) |
| Page | pp. 79 - 84 |
| Keyword | High level synthesis, resource sharing, resource binding, process variation |
| Abstract | As technology scales, the delay uncertainty caused
by process variations has become increasingly pronounced in
deep submicron designs. In the presence of process variations,
worst-case timing analysis may lead to overly conservative
synthesis, and may end up using excess resources to guarantee
design constraints. In this paper, we propose an efficient
variation-aware resource sharing and binding algorithm in
behavioral synthesis, which takes into account the performance
variations for functional units. The performance yield, which
is defined as the probability that the synthesized hardware
meets the target performance constraints, is used to evaluate the
synthesis result. An efficient metric called statistical performance
improvement, is used to guide resource sharing and binding. The
proposed algorithm is integrated into a commercial synthesis
framework that transfer design specifications from behavioral
description to RTL netlists. The effectiveness of the proposed
algorithm is demonstrated with a set of industrial benchmark
designs, which consist of blocks that are commonly used in
wireless and image processing applications. The experimental
results show that our method achieves an average 33% area
reduction over traditional methods, which are based on the
worst-case delay analysis, with an average 10% run time
overhead. |
| Title | Peak Temperature Control in Thermal-aware Behavioral Synthesis through Allocating the Number of Resources |
| Author | *Junbo Yu, Qiang Zhou, Jinian Bian (Tsinghua University, China) |
| Page | pp. 85 - 90 |
| Keyword | resource usage allocation, behavioral synthesis, peak temperature |
| Abstract | High temperature adversely impacts on reliability, performance, and leakage power of ICs. In behavioral synthesis, both resource usage allocation and resource binding influence the final thermal profile. Previous thermal-aware behavioral syntheses only focused on binding, ignoring allocation. This paper proposes thermal-aware behavioral synthesis with resource usage allocation. According to power density and feedbacks from thermal simulation, we allocate the number of resources under area constraint. Our flow effectively controls peak temperature and creates even power densities among resources of gdifferenth and gsameh types. Compared to classic behavioral synthesis of peak temperature control, our technique reduces peak temperature by 11.1 on average with no area overhead and only 1.2 more steps latency overhead. |