(Back to Session Schedule)

The 14th Asia and South Pacific Design Automation Conference

Session 2C  Logic and Arithmetic Optimization
Time: 13:30 - 15:35 Tuesday, January 20, 2009
Location: Room 414+415
Chairs: Dale Edwards (Semiconductor Research Corp., United States), Hiroyuki Higuchi (Fujitsu Microelectronics Ltd., Japan)

2C-1 (Time: 13:30 - 13:55)
TitleSAT-Controlled Redundancy Addition and Removal --- A Novel Circuit Restructuring Technique
AuthorChi-An Wu, Ting-Hao Lin, Shao-Lun Huang, *Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Pagepp. 191 - 196
Detailed information (abstract, keywords, etc)

2C-2 (Time: 13:55 - 14:20)
TitleOn Improved Scheme for Digital Circuit Rewiring and Application on Further Improving FPGA Technology Mapping
AuthorFu Shing Chim, *Tak Kei Lam, Yu Liang Wu (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 197 - 202
Detailed information (abstract, keywords, etc)
Slides

2C-3 (Time: 14:20 - 14:45)
TitleHybrid LZA: A Near Optimal Implementation of the Leading Zero Anticipator
AuthorAmit Verma (National Inst. of Tech., Rourkela, India), *Ajay K. Verma, Philip Brisk, Paolo Ienne (EPFL, Switzerland)
Pagepp. 203 - 209
Detailed information (abstract, keywords, etc)

2C-4 (Time: 14:45 - 15:10)
TitleAn Optimized Design for Serial-Parallel Finite Field Multiplication over GF(2m) Based on All-One Polynomials
AuthorPramod Kumar Meher (Nanyang Technological Univ., Singapore), *Yajun Ha (National Univ. of Singapore, Singapore), Chiou-Yng Lee (Lunghwa Univ. of Science and Tech., Taiwan)
Pagepp. 210 - 215
Detailed information (abstract, keywords, etc)