| Title | SAT-Controlled Redundancy Addition and Removal --- A Novel Circuit Restructuring Technique |
| Author | Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, *Chung-Yang (Ric) Huang (National Taiwan University, Taiwan) |
| Page | pp. 191 - 196 |
| Keyword | Redundancy Addition and Removal, SAT, Logic Restructuring |
| Abstract | We proposed a novel Boolean Satisfiability (SAT)-controlled redundancy addition and removal (RAR) algorithm to resolve the performance and quality problems of the previous RAR approaches. With the introduction of modern SAT techniques, such as efficient Boolean constraint propagation (BCP), conflict-driven learning, and flexible decision procedure, our RAR engine can identify 10x more alternative wires/gates while achieving 70% reduction in runtime. |
| Title | On Improved Scheme for Digital Circuit Rewiring and Application on Further Improving FPGA Technology Mapping |
| Author | Fu Shing Chim, *Tak Kei Lam, Yu Liang Wu (The Chinese University of Hong Kong, Hong Kong) |
| Page | pp. 197 - 202 |
| Keyword | Rewiring, Graph-based, FPGA, Technology Mapping, VLSI CAD |
| Abstract | The digital circuit rewiring technique has been shown to be one of the most powerful logic transformation methods being able to further improve some already excellent results on many EDA problems. In this work a new hybrid rewiring approach that can enjoy advantages from both ATPG-based and graph-based rewiring is proposed. Our hybrid approach utilizes structural characteristics and ATPG technique to perform quick alternative wires identification inside circuits. Experimental results suggest that our hybrid engine is able to achieve about 50% of alternative wires coverage when compared with ATPG-based rewiring engine with 4% of runtime only. For some problems only requiring a good-enough and very quick solution, this new rewiring technique may serve as a useful alternative. |
| Slides |
| Title | Hybrid LZA: A Near Optimal Implementation of the Leading Zero Anticipator |
| Author | Amit Verma (National Institute of Technology, Rourkela, India), *Ajay K. Verma, Philip Brisk, Paolo Ienne (Ecole Polytechnique Federale de Lausanne, Switzerland) |
| Page | pp. 203 - 209 |
| Keyword | leading zero anticipator, Error detection, Adder |
| Abstract | The Leading Zero Anticipator (LZA) is one of the main components used
in floating point addition. It tends to be on the critical path, so it has attracted the attention of many researchers in the past. Most LZAs used today can be classified in two categories: exact and inexact. Inexact LZAs are normally preferred due to their shorter critical paths and reduced complexity; however, the inexact LZA requires an additional correct stage. In this paper we present a new LZA architecture that combines ideas taken from prior exact and inexact LZAs.Our new LZA improves the delay of floating point addition by 7-10% compared to state of art techniques as well as reduces hardware area in most cases. We also establish theoretical lower bounds on the delay of an LZA and we show that our LZA is very close to these bounds. |
| Title | An Optimized Design for Serial-Parallel Finite Field Multiplication over GF(2m) Based on All-One Polynomials |
| Author | Pramod Kumar Meher (Nanyang Technological University, Singapore), *Yajun Ha (National University of Singapore, Singapore), Chiou-Yng Lee (Lunghwa University of Science and Technology, Taiwan) |
| Page | pp. 210 - 215 |
| Keyword | finite field multiplication, VLSI, architecture optimization |
| Abstract | In this paper, we derive a recursive algorithm for finite field multiplication over GF(2^m) based on irreducible all-one-polynomials (AOP), where the modular reduction of degree is achieved by cyclic left-shift without any logic operations. A regular and localized bit level dependence graph (DG) is derived from the proposed algorithm and mapped into an array architecture, where the modular reduction is achieved by a serial-in parallel-out shift-register. The multiplier is optimized further to perform the accumulation of partial products by the T flip flops of the output register without XOR gates. It is interesting to note that the optimized structure consists of an array of (m+1) AND gates between an array of (m+1) D flip flops and an array of (m+1) T flip flops. The proposed structure therefore involves significantly less area and less computation time compared with the corresponding existing structures. |