| Title | System-Level Cost Analysis and Design Exploration for Three-Dimensional Integrated Circuits (3D ICs) |
| Author | *Xiangyu Dong, Yuan Xie (Pennsylvania State University, United States) |
| Page | pp. 234 - 241 |
| Keyword | 3D Integration, Cost Analysis |
| Abstract | Three-dimensional integrated circuit (3D IC) is emerging as an attractive option for overcoming the barriers in interconnect scaling. The majority of the existing 3D IC research is focused on how to take advantage of the performance, power, smaller form-factor, and heterogeneous integration benefits that offered by 3D integration. However, all such advantages ultimately have to translate into cost savings when a design strategy has to be decided: Is 3D integration a cost effective way for a particular IC design? Consequently, system-level cost analysis at the early design stage is imperative to help the decision making on whether 3D integration should be adopted. In this paper, we study the design estimation method for 3D ICs at the early design stage, and propose a cost analysis model to study the cost implication for 3D ICs, and address the following cost-related problems related to 3D IC design: (1) Do all the benefits of 3D IC design come with a much higher cost? (2) How to do 3D integration in a cost-effective way? (3)Are there any design options to compensate the extra 3D bonding cost? A cost-driven 3D IC design flow is also proposed to guide the design space exploration for 3D ICs toward a costeffective direction. |
| Title | Synthesis of Networks on Chips for 3D Systems on Chips |
| Author | *Srinivasan Murali, Ciprian Seiculescu (Ecole Polytechnique Federale de Lausanne, Switzerland), Luca Benini (University of Bologna, Italy), Giovanni De Micheli (Ecole Polytechnique Federale de Lausanne, Switzerland) |
| Page | pp. 242 - 247 |
| Keyword | Networks on Chips, 3D, topology, synthesis |
| Abstract | Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Designing power efficient NoCs for 3D SoCs that satisfy the application performance requirements, while satisfying the 3D technology constraints is a big challenge. In this work, we address this problem and present a synthesis approach for designing power-performance efficient 3D NoCs. We present methods to determine the best topology, compute paths and perform placement of the NoC components in each 3D layer. We perform experiments on varied, realistic SoC benchmarks to validate the methods and also perform a comparative study of the resulting 3D NoC designs with 3D optimized mesh topologies. The NoCs designed by our synthesis method results in large interconnect power reduction (average of 38%) and latency reduction (average of 25%) when compared to traditional NoC designs. |
| Title | System-Level Process Variability Compensation on Memory Organizations. On the Scalability of Multi-Mode Memories |
| Author | *Concepción Sanz, Manuel Prieto, José Ignacio Gómez (Universidad Complutense de Madrid, Spain), Antonis Papanikolaou, Francky Catthoor (Inter-University Microelectronics Center, Belgium) |
| Page | pp. 254 - 259 |
| Keyword | Process variation, parametric yield, variability compensation |
| Abstract | Process variation and the dynamism of modern applications
can degrade the expected performance of a system. Execution
time can be severely affected by both factors, resulting in
deadline violations and energy consumption overheads. Memory
organizations, which account for a large part of the system-energy
and the time budgets, are especially vulnerable to process variation.
Configurable – multi-mode – memories are a promising technology
to deal with these problems, but they also introduce new
issues that need to be solved. Essentially, adding configuration
capabilities to the memories comes with a cost, both in memory
area and control complexity; hence, we need to evaluate what is
the minimum amount of re-configurability to satisfy system’s constraints.
In this paper, we analyze the scalability of configurable
memories and highlight the relationship among mode allocation,
memory mapping and data allocation. |
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