| Title | Efficient Analytical Determination of the SEU-induced Pulse Shape |
| Author | Rajesh Garg, *Sunil P. Khatri (Texas A&M University, United States) |
| Page | pp. 461 - 467 |
| Keyword | Radiation, Single Event Upset, Single Even Transients |
| Abstract | Single event upsets (SEUs) have become problematic for both combinational and sequential circuits in the deep sub-micron era due to device scaling, lowered supply voltages and higher operating frequencies. To design radiation tolerant circuits efficiently, techniques are required to analyze the effects of a radiation particle strike on a circuit early in the design flow, and hence evaluate the circuit's resilience to SEU events. For an accurate estimation of the SEU tolerance of a circuit, it is important to consider the effects of electrical masking. This is typically done by performing circuit simulations, which are slow. In this paper, we present an analytical model for the determination of the shape of radiation-induced voltage glitches in combinational circuits. The output of our approach can be propagated to the primary outputs of the circuit using existing tools, thereby modeling the effects of electrical masking. This enables an accurate and quick evaluation of the SEU robustness of a circuit. Experimental results demonstrate that our model is very accurate, with a very low root mean square percentage error in the estimation of the shape of the voltage glitch of (4.5%) compared to SPICE. Our model gains its accuracy by using a non-linear model for the load current of the gate, and by considering the effect of the ion track establishment constant on the radiation induced voltage glitch. Our analytical model is very fast (275X faster than SPICE) and accurate, and can therefore be easily incorporated in a design flow to estimate the SEU tolerance of circuits early in the design process. |
| Title | Post-Routing Redundant Via Insertion with Wire Spreading Capability |
| Author | Cheok-Kei Lei, *Po-Yi Chiang, Yu-Min Lee (National Chiao Tung University, Taiwan) |
| Page | pp. 468 - 473 |
| Keyword | redundant via insertion, wire spreading, DFM, yield |
| Abstract | Redundant via insertion is a widely recommended technique to enhance the via yield and reliability. In this paper, the post-routing redundant via insertion problem is transformed to a mixed bipartite-conflict graph matching problem, and an efficient heuristic minimum weighted matching (HMWM) algorithm is presented to solve it. The developed method not only inserts redundant vias for alive vias but also protects the dead vias by utilizing the wire spreading capability-that's to say, the method shifts wires into the empty space and adds redundant vias for dead vias to further enhance the via yield. Experimental results show that the average insertion rate of alive vias is 99.54% with a short run time, and the wire spreading technique can achieve average insertion rate to be 54.41% for dead vias. |
| Title | Accounting for Non-linear Dependence Using Function Driven Component Analysis |
| Author | Lerong Cheng, *Puneet Gupta, Lei He (University of California, Los Angeles, United States) |
| Page | pp. 474 - 479 |
| Keyword | Noice margin, Statistical Analysis |
| Abstract | Majority of practical multivariate statistical analyses and optimizations model interdependence among random variables in terms of the linear correlation among them. Though linear correlation is simple to use and evaluate, in several cases non-linear dependence between random variables may be too strong to ignore. In this paper, We propose polynomial correlation coefficients as simple measure of multi-variable non-linear dependence and show that need for modeling non-linear dependence strongly depends on the end function that is to be evaluated from the random variables. Then, we calculate the errors in estimation which result from assuming independence of components generated by linear de-correlation techniques such as PCA and ICA. The experimental result shows that the error predicted by our method is within 1% error compared to the real simulation. In order to deal with non-linear dependence, we further develop a target function driven component analysis algorithm (FCA) to minimize the error caused by ignoring high order dependence and apply such technique to statistical leakage power analysis and SRAM cell noise margin variation analysis. Experimental results show that the proposed FCA method is more accurate compared to the traditional PCA or ICA. |
| Title | Risk Aversion Min-Period Retiming under Process Variations |
| Author | Jia Wang, *Hai Zhou (Northwestern University, United States) |
| Page | pp. 480 - 485 |
| Keyword | statistical optimization, retiming, process variations |
| Abstract | Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variables. It remains a challenge problem to apply such results in order to address the variability in circuit optimizations. In this paper, we study the statistical retiming problem, where retiming is a powerful sequential transformation that relocates flip-flops in a circuit without changing its functionality. We formulate the risk aversion min-period retiming problem under process variations based on conventional two-stage stochastic program with fixed recourse and a risk aversion objective of the clock period. We prove that the proposed problem is an integer convex program, show that the subgradient of the objective function can be derived from the combinational paths with the maximum path delay, and present a heuristic incremental algorithm to solve the proposed problem. Our approach can handle arbitrary gate delay model under process variations through sampling from a black-box and the effectiveness is confirmed by the experimental results. Further more, we point out how the current state-of-the-art SSTA techniques could be improved for future optimization algorithms when analytical models are available. |
| Title | Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning Lithography |
| Author | Kwangok Jeong, *Andrew B. Kahng (University of California, San Diego, United States) |
| Page | pp. 486 - 491 |
| Keyword | Bimodal, DPL, Double patterning, CD |
| Abstract | Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes and prints the shapes of a critical-layer layout in two exposures. In traditional single-exposure lithography, adjacent identical layout features will have identical mean critical dimension (CD), and spatially correlated CD variations. However, with DPL, adjacent features can have distinct mean CDs, and uncorrelated CD variations. This introduces a new set of `bimodal' challenges for timing analysis and optimization. We assess the potential impact of DPL on timing analysis error and guardbanding, and find that the traditional `unimodal' characterization and analysis framework may not be viable for DPL. For example, using 45nm models, we find that different DPL mask layout solutions can cause 50ps skew in clock distribution that is unseen by traditional analyses. Different mask layouts can also result in 20\% or more change in timing path delays. Such results lead to insights into physical design optimizations for clock and data path placement and mask coloring that can help mitigate the error and guardband costs of DPL. |
| Title | Scheduled Voltage Scaling for Increasing Lifetime in the Presence of NBTI |
| Author | *Lide Zhang, Robert Dick (Northwestern University, United States) |
| Page | pp. 492 - 497 |
| Keyword | Scheduled Voltage Scaling, Negative Bias Temperature Instability (NBTI), Guard Banding |
| Abstract | Negative Bias Temperature Instability (NBTI) is a leading reliability concern for integrated circuits (ICs). It increases the threshold voltages of PMOS transistors, thereby increasing delay. We propose the use of scheduled voltage scaling that gradually enhances the operating voltage of the IC to compensate for NBTI-related performance degradation. Scheduled voltage scaling has the potential to increase IC lifetime by 46% relative to the conventional approach using guard banding for ICs fabricated using a 45nm process. |